74HCT157PW ,74HC/HCT157; Quad 2-input multiplexerGENERAL DESCRIPTIONvariables with one variable common.The 74HC/HCT157 are high-speed Si-gate CMOS d ..
74HCT158 ,inverting
74HCT158D ,Quad 2-input multiplexer; inverting
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74HCT161 ,asynchronous reset
74HCT161D ,Presettable synchronous 4-bit binary counter; asynchronous resetGENERAL DESCRIPTIONThe look-ahead carry simplifies serial cascading of thecounters. Both count enab ..
74VHC14MTCX ,Hex Schmitt InverterFeaturesThe VHC14 is an advanced high speed CMOS Hex
74HC157PW-74HCT157DB-74HCT157N-74HCT157PW
74HC/HCT157; Quad 2-input multiplexer
Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
FEATURES Non-inverting data path Output capability: standard ICC category: MSI
GENERAL DESCRIPTIONThe 74HC/HCT157 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT157 are quad 2-input multiplexers which
select 4 bits of data from two sources under the control of
a common data select input (S). The four outputs present
the selected data in the true (non-inverted) form. The
enable input (E) is active LOW. WhenE is HIGH, all of the
outputs (1Y to 4Y) are forced LOW regardless of all other
input conditions.
Moving the data from two groups of registers to four
common output buses is a common use of the “157”. The
state of the common data select input (S) determines the
particular register from which the data comes. It can also
be used as function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
The “157” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations are:
1Y = E.(1l1.S+ 1l0.S)
2Y = E.(2l1.S+ 2l0.S)
3Y = E.(3l1.S+ 3l0.S)
4Y = E.(4l1.S+ 4l0.S)
The “157” is identical to the “158” but has non-inverting
(true) outputs.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes CPD is used to determine the dynamic power dissipation (PDin μW): = CPD× VCC2×fi+∑ (CL× VCC2×fo) where: = input frequency in MHz = output frequency in MHz (CL× VCC2×fo) = sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC− 1.5 V
Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
PIN DESCRIPTION
Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
FUNCTION TABLE
Notes H = HIGH voltage level
L = LOW voltage level
X = don’t care
Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HCGND = 0 V; tr = tf = 6 ns; CL = 50 pF
Philips Semiconductors Product specification
Quad 2-input multiplexer 74HC/HCT157
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT typesThe value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCTGND = 0 V; tr = tf = 6 ns; CL = 50 pF
