74HC157D-74HC157N-74HC157PW-74HCT157D Fast Delivery |IC PHOENIX CO.,LIMITED

74HC157D ,Quad 2-input multiplexerPin configuration DIP16, SO16, (T)SSOP16 Fig 6.
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74HC157PW ,74HC/HCT157; Quad 2-input multiplexer 74HC157; 74HCT157Quad 2-input multiplexerRev. 6 — 27 August 2012 Product data sheet1.
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74LVC08ADB ,Quad 2-input AND gateLOGIC DIAGRAM (ONE GATE)A&132 YB&4SV0041565&98FUNCTION TABLE10INPUTS OUTPUTS&121113nA nB nYSV00436 ..
74LVC08AM ,LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE HIGH PERFORMANCEapplications.■ ESD PERFORMANCE: It can be interfaced to 5V signal environment forHBM > 2000V (MIL S ..
74LVC08AMTR ,LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE HIGH PERFORMANCEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LVC08APW ,Quad 2-input AND gatePIN CONFIGURATION LOGIC SYMBOL1A1A 1 14 1VCC 1Y31B21B 2 13 4B2A42Y1Y 3 12 4A62B52A 4 11 4Y3A93Y83B2 ..

74HC157D-74HC157N-74HC157PW-74HCT157D
Quad 2-input multiplexer
1. General description
The 74HC157; 74HCT157 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT157 are quad 2-input multiplexers which select 4 bits of data from two
sources under the control of a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs (1Yto 4Y) are forced LOW regardless of
all other input conditions.
Moving the data from two groups of registers to four common output buses is a common
use of the 74HC/HCT157. The state of the common data select input (S) determines the
particular register from which the data comes. It can also be used as function generator.
The device is useful for implementing highly irregular logic by generating any four of the
16 different functions of two variables with one variable common. The 74HC/HCT157 is
logic implementation of a 4-pole, 2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations are:= E (1I1 S+ 1I0 S)= E (2I1 S+ 2I0 S)= E (3I1 S+ 3I0 S)= E (4I1 S+ 4I0 S)
The 74HC/HCT157 is identical to the 74HC158 but has non-inverting (true) outputs.
2. Features and benefits Low-power dissipation Non-inverting data path ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-A exceeds 200V Specified from 40 Cto+85 C and from 40 Cto+125C
74HC157; 74HCT157
Quad 2-input multiplexer
Rev. 6 — 27 August 2012 Product data sheet
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74HC157N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT157N
74HC157D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
74HCT157D
74HC157DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT157DB
74HC157PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT157PW
74HC157BQ 40Cto +125C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
74HCT157BQ
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
5. Pinning information
5.1 Pinning
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
5.2 Pin description
6. Functional description
[1] H= HIGH voltage level;= LOW voltage level;= don’t care.
7. Limiting values
[1] Ptot derates linearly with 8 mW/K above 70C.
[2] Ptot derates linearly with 5.5 mW/K above 60C.
Table 2. Pin description 1 common data select input
1I0 to 4I0 2, 5, 11, 14 data inputs from source 0
1I1 to 4I1 3, 6, 10, 13 data inputs from source 1
1Y to 4Y 4, 7, 9, 12 multiplexer outputs
GND 8 ground (0V) 15 enable input (active LOW)
VCC 16 supply voltage
Table 3. Function table[1] XXXL
LLLX L
LLH X H X LL X H H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI >VCC +0.5 V - 20 mA
IOK output clamping current VO< 0.5 V or VO >VCC +0.5V - 20 mA output current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125C
SO16 package [1]- 500 mW
TSSOP16 package [2]- 500 mW
DHVQFN16 package [3]- 500 mW
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
[3] Ptot derates linearly with 4.5 mW/K above 60C.
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V --83 - --ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC157
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage =VIHorVIL= 20 A; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= 20 A; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= 20 A; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= 4.0 mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= 5.2 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage =VIHorVIL =20 A; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 A; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V= 4.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V= 5.2 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V 0.1 - 1.0 - 1.0 A
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
ICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 A input
capacitance
-3.5 - pF
74HCT157
VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V= 20A 4.4 4.5 - 4.4 - 4.4 - V=4 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V =20A - 0 0.1 - 0.1 - 0.1 V= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =5.5V 0.1 - 1.0 - 1.0 A
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 A
ICC additional
supply current =VCC 2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V; =0A
per input pin; nIn inputs - 100 360 - 450 - 490 A
per input pin; E input - 60 216 - 270 - 294 A
per input pin; S input - 100 360 - 450 - 490 A input
capacitance
-3.5 - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
10. Dynamic characteristicsTable 7. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure9.
For type 74HC157
tpd propagation
delay
nI0, nI1 to nY; see Figure7 [1]
VCC = 2.0 V - 36 125 - 155 - 190 ns
VCC = 4.5 V - 13 25 - 31 - 38 ns
VCC =5V; CL =15pF - 11 - - - - - ns
VCC = 6.0 V - 10 21 - 26 - 32 ns
S to nY; see Figure7 [1]
VCC = 2.0 V - 41 125 - 155 - 190 ns
VCC = 4.5 V - 15 25 - 31 - 38 ns
VCC =5V; CL =15pF - 12 - - - - - ns
VCC = 6.0 V - 12 21 - 26 - 32 nsto nY; see Figure8 [1]
VCC = 2.0 V - 39 115 - 145 - 175 ns
VCC = 4.5 V - 14 23 - 29 - 35 ns
VCC =5V; CL =15pF - 11 - - - - - ns
VCC = 6.0 V - 11 20 - 25 - 30 ns transition
time
nY; see Figure7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC
[3] -70 - - - - - pF
For type 74HCT157
tpd propagation
delay
nI0, nI1 to nY; see Figure7 [1]
VCC = 4.5 V - 16 27 - 34 - 41 ns
VCC =5V; CL =15pF - 13 - - - - - ns
S to nY; see Figure7 [1]
VCC = 4.5 V - 22 37 - 46 - 56 ns
VCC =5V; CL =15pF - 19 - - - - - nsto nY; see Figure8 [1]
VCC = 4.5 V - 15 26 - 33 - 39 ns
VCC =5V; CL =15pF - 12 - - - - - ns
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of outputs.
11. Waveforms transition
time
nY; see Figure7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC
[3] -70 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure9.
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
Table 8. Measurement points
74HC157 0.5VCC 0.5VCC
74HCT157 1.3V 1.3V
NXP Semiconductors 74HC157; 74HCT157
Quad 2-input multiplexer
Table 9. Test data
74HC157 VCC 6.0 ns 15 pF, 50pF tPLH, tPHL
74HCT157 3.0V 6.0 ns 15 pF, 50pF tPLH, tPHL

Partno	Mfg	Dc	Qty	Available	Descript
74HC157D	NXP	N/a	63210	avai	Quad 2-input multiplexer
74HC157N	TI	N/a	5000	avai	Quad 2-input multiplexer
74HC157PW	NXP	N/a	15000	avai	74HC/HCT157; Quad 2-input multiplexer
74HC157PW		N/a	15000	avai	74HC/HCT157; Quad 2-input multiplexer
74HCT157D		N/a	1400	avai	74HC/HCT157; Quad 2-input multiplexer