74HC148 ,8-3 Line Priority EncoderMM74HC148 8-3 Line Priority EncoderOctober 1987Revised February 1999MM74HC1488-3 Line Priority Enco ..
74HC14D ,74HC/HCT14; Hex inverting Schmitt triggerPin configuration DIP14, SO14 and (T)SSOP14 Fig 5.
74HC14DB ,Hex inverting Schmitt triggerINTEGRATED CIRCUITSDATA SHEET74HC14; 74HCT14Hex inverting Schmitt triggerProduct specification 2003 ..
74HC14DB ,Hex inverting Schmitt triggerINTEGRATED CIRCUITSDATA SHEET74HC14; 74HCT14Hex inverting Schmitt triggerProduct specification 2003 ..
74HC14DR2G , Hex Schmitt−Trigger Inverter High−Performance Silicon−Gate CMOS
74HC14DR2G , Hex Schmitt−Trigger Inverter High−Performance Silicon−Gate CMOS
74LV573DB ,Octal D-type transparent latch 3-StateINTEGRATED CIRCUITS74LV573Octal D-type transparent latch (3-State)Product specification 1998 Jun 10 ..
74LV573PW ,Octal D-type transparent latch 3-StateINTEGRATED CIRCUITS74LV573Octal D-type transparent latch (3-State)Product specification 1998 Jun 10 ..
74LV574 ,positive edge-trigger (3-State)
74LV574A , OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
74LV574D ,Octal D-type flip-flop; positive edge-trigger 3-State74LV574Octal D-type flip-flop; positive edge-trigger; 3-stateRev. 04 — 14 May 2009 Product data sheet ..
74LV574D ,Octal D-type flip-flop; positive edge-trigger 3-Stateapplications. A clock (CP) and an outputenable (OE) input are common to all flip-flops. It is a low-v ..
74HC148
8-3 Line Priority Encoder
MM74HC148 8-3 Line Priority Encoder October 1987 Revised February 1999 MM74HC148 8-3 Line Priority Encoder external circuitry. All data inputs and outputs are active at General Description the low logic level. The MM74HC148 priority encoder utilizes advanced sili- All inputs are protected from damage due to static dis- con-gate CMOS technology. It has the high noise immunity charge by internal diode clamps to V and ground. CC and low power consumption typical of CMOS circuits, as well as the speeds and output drive similar to LB-TTL. Features This priority encoder accepts 8 input request lines 0–7 and outputs 3 lines A0–A2. The priority encoding ensures that � Typical propagation delay: 13 ns only the highest order data line is encoded. Cascading cir- � Wide supply voltage range: 2V–6V cuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for Ordering Code: Order Number Package Number Package Description MM74HC148M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC148MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC148N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Inputs Outputs Pin Assignments for DIP, SOIC and TSSOP EI 012 345 67 A2 A1 A0 GS EO H XXX XXX XX H H H H H L H H HHH HHH H H H H L L XXX XXX X L L L L L H L XXX XXX L H L L H L H L XXX XX L H H L H L L H L XXX X L H H H L H H L H L XXX L H H H H H L L L H L X X L HH HHH H L H L H L X L HHH HHH H H L L H L L H HHH HHH H H H L H H = HIGH L = LOW X = Irrelevant © 1999 DS009390.prf
