74HC138BQ-74HC138D-74HC138DB-74HC138PW-74HCT138D-74HCT138PW Fast Delivery |IC PHOENIX CO.,LIMITED

74HC138PW ,3-to-8 line decoder, demultiplexer; invertingPin configuration DIP16, SO16, SSOP16 and Fig 5.
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74LV373 ,OCTAL D-TYPE TRANSPARENT LATCH(3-State)
74LV373D ,Octal D-type transparent latch (3-State)PIN CONFIGURATION LOGIC SYMBOL111 20 VOECC2 19 QQ0 7 LE3D Q 20 0D 3 18 D0 74 D 5Q1 14D 17 D1 667 D ..
74LV373DB ,Octal D-type transparent latch 3-StatePIN CONFIGURATION LOGIC SYMBOL111 20 VOECC2 19 QQ0 7 LE3D Q 20 0D 3 18 D0 74 D 5Q1 14D 17 D1 667 D ..
74LV373PW ,Octal D-type transparent latch (3-State)INTEGRATED CIRCUITS74LV373Octal D-type transparent latch (3-State)Product specification 1998 Jun 10 ..
74LV374 ,positive edge-trigger (3-State)
74LV374 ,positive edge-trigger (3-State)

74HC138BQ-74HC138D-74HC138DB-74HC138PW-74HCT138D-74HCT138PW
3-to-8 line decoder, demultiplexer; inverting
1. General description
The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1
and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0to Y7).
The 74HC138; 74HCT138 features three enable inputs: two active LOW (E1 and E2) and
one active HIGH (E3). Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the 74HC138; 74HCT138
to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138; 74HCT138 ICs and one
inverter.
The 74HC138; 74HCT138 can be used as an eight output demultiplexer by using one of
the active LOW enable inputs as the data input and the remaining enable inputs as
strobes. Permanently tie unused enable inputs to their appropriate active HIGH- or
LOW-state.
The 74HC138; 74HCT138 is identical to the 74HC238; 74HCT238 but has inverting
outputs.
2. Features and benefits Demultiplexing capability Multiple input enable for easy expansion Complies with JEDEC standard no. 7A Ideal for memory chip select decoding Active LOW mutually exclusive outputs ESD protection: HBM EIA/JESD22-A114F exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V Multiple package options Specified from −40 °Cto+85 °C and from −40 °Cto+125°C
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 4 — 27 June 2012 Product data sheet
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
4. Functional diagram
Table 1. Ordering information
74HC138N −40 °Cto+125°C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT138N
74HC138D −40 °Cto+125°C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74 HCT138D
74HC138DB −40 °Cto+125°C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HCT138DB
74HC138PW −40 °Cto+125°C TSSOP16 plastic thin shrink small outline package; leads; body width 4.4 mm
SOT403-1
74HCT138PW
74HC138BQ −40 °Cto+125°C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; terminals; body 2.5× 3.5 × 0.85 mm
SOT763-1
74HCT138BQ
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
5.2 Pin description
6. Functional description
[1] H= HIGH voltage level;= LOW voltage level;= don’t care.
7. Limiting values
Table 2. Pin description
A0, A1, A2 1, 2, 3 address input A0, A1, A2
E1, E2 4, 5 enable input E1, E2 (active LOW) 6 enable input E3 (active HIGH)
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 15, 14, 13, 12, 11, 10, 9, 7 output Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 (active LOW)
GND 8 ground (0V)
VCC 16 positive supply voltage
Table 3. Function table[1] XXXX XH H H H H H H H X L L H L L L HH HH HH HL L H H HH HH HL H LH H H H H L H H H H H HH HL HH H L L H HH L H HH H L H H HL HH HH H H L H L H HH HH H H H L HH HH HH H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI >VCC +0.5 V - ±20 mA
IOK output clamping current VO< −0.5 V or VO >VCC +0.5V - ±20 mA output current VO = −0.5 V to (VCC +0.5V) - ±25 mA
ICC quiescent supply current - 50 mA
IGND ground current - −50 mA
Tstg storage temperature −65 +150 °C
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C.
[4] For DHVQFN16 packages: Ptot derates linearly with 4.5 mW/K above 60°C.
8. Recommended operating conditions
9. Static characteristics
Ptot total power dissipation
DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW
SSOP16 package [3]- 500 mW
TSSOP16 package [3]- 500 mW
DHVQFN16 package [4]- 500 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0V)
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0- VCC V output voltage 0 - VCC 0- VCC V
Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
74HC138
VIH HIGH-level
input voltage
VCC= 2.0V 1.5 1.2 - 1.5 - 1.5 - V
VCC= 4.5V 3.15 2.4 - 3.15 - 3.15 - V
VCC= 6.0V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage
VCC= 2.0V - 0.8 0.5 - 0.5 - 0.5 V
VCC= 4.5V - 2.1 1.35 - 1.35 - 1.35 V
VCC= 6.0V - 2.8 1.8 - 1.8 - 1.8 V
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
VOH HIGH-level
output voltage =VIHorVIL= −20 μA; VCC= 2.0V 1.9 2.0 - 1.9 - 1.9 - V= −20 μA; VCC= 4.5V 4.4 4.5 - 4.4 - 4.4 - V= −20 μA; VCC= 6.0V 5.9 6.0 - 5.9 - 5.9 - V= −4.0 mA; VCC= 4.5V 3.98 4.32 - 3.84 - 3.7 - V= −5.2 mA; VCC= 6.0V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage =VIHorVIL =20 μA; VCC= 2.0V - 0 0.1 - 0.1 - 0.1 V =20 μA; VCC= 4.5V - 0 0.1 - 0.1 - 0.1 V =20 μA; VCC= 6.0V - 0 0.1 - 0.1 - 0.1 V= 4.0 mA; VCC= 4.5V - 0.15 0.26 - 0.33 - 0.4 V= 5.2 mA; VCC= 6.0V - 0.16 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =6.0V ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
per input pin; VI =VIHor VIL; =VCC or GND;
other inputs at VCC or GND;
VCC =6.0 V; IO =0A ±0.5 - ±5.0 - ±10
ICC supply current VI =VCCor GND; IO =0A;
VCC =6.0V - 8.0 - 80 - 160 μA input
capacitance
-3.5 - pF
74HCT138
VIH HIGH-level
input voltage
VCC= 4.5 V to 5.5V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage
VCC= 4.5 V to 5.5V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage =VIHor VIL; VCC =4.5V= −20μA 4.4 4.5 - 4.4 - 4.4 - V=−4 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage =VIHor VIL; VCC =4.5V =20μA - 0 0.1 - 0.1 - 0.1 V= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V input leakage
current =VCCor GND;
VCC =5.5V ±0.1 - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
per input pin; VI =VIHor VIL; =VCC or GND;
other inputs at VCC or GND;
VCC =5.5 V; IO =0A ±0.5 - ±5.0 - ±10
ICC supply current VI =VCCor GND; IO =0A;
VCC =5.5V - 8.0 - 80 - 160 μA
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
10. Dynamic characteristics
ΔICC additional
supply current =VCC− 2.1V;
other inputs at VCCor GND;
VCC= 4.5Vto 5.5V; =0A
per input pin; An inputs - 150 540 - 675 - 735 μA
per input pin; En inputs - 125 450 - 562.5 - 612.5 μA
per input pin; E3 input - 100 360 - 450 - 490 μA input
capacitance
-3.5 - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure8.
For type 74HC138
tpd propagation
delayto Yn; see Figure6 [1]
VCC = 2.0 V - 41 150 - 190 - 225 ns
VCC = 4.5 V - 15 30 - 38 - 45 ns
VCC =5V; CL =15pF - 12 - - - - - ns
VCC = 6.0 V - 12 26 - 33 - 38 ns
E3 to Yn; see Figure6 [1]
VCC = 2.0 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 20 - 38 - 45 ns
VCC =5V; CL =15pF - 14 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
Ento Yn; see Figure7 [1]
VCC = 2.0 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 20 - 38 - 45 ns
VCC =5V; CL =15pF - 14 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns transition
time
Yn; see Figure 6 and
Figure7
[2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC
[3] -67 - - - - - pF
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW). =CPD× VCC2×fi×N+ (CL× VCC2× fo) where:
fi = input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC = supply voltage in V;= number of inputs switching;
(CL× VCC2×fo)= sum of outputs.
For type 74HCT138
tpd propagation
delayto Yn; see Figure6 [1]
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC =5V; CL =15pF - 17 - - - - - ns
E3 to Yn; see Figure6 [1]
VCC = 4.5 V - 18 40 - 50 - 60 ns
VCC =5V; CL =15pF - 19 - - - - - ns
Ento Yn; see Figure7 [1]
VCC = 4.5 V - 19 40 - 50 - 60 ns
VCC =5V; CL =15pF - 19 - - - - - ns transition
time
Yn; see Figure 6 and
Figure7
[2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
CPD power
dissipation
capacitance =50pF;f= 1 MHz; =GNDto VCC
[3] -67 - - - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground =0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure8.
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
11. Waveforms
Table 8. Measurement points
74HC138 0.5VCC 0.5VCC
74HCT138 1.3V 1.3V
NXP Semiconductors 74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Table 9. Test data
74HC138 VCC 6ns 15pF, 50 pF 1 kΩ open GND VCC
74HCT138 3V 6ns 15 pF, 50 pF 1 kΩ open GND VCC

Partno	Mfg	Dc	Qty	Available	Descript
74HC138BQ	NXP	N/a	400	avai	3-to-8 line decoder, demultiplexer; inverting
74HC138D	HIT	N/a	7	avai	3-to-8 line decoder, demultiplexer; inverting
74HC138DB	NXP	N/a	13368	avai	3-to-8 line decoder, demultiplexer; inverting
74HC138PW	NXP	N/a	55741	avai	3-to-8 line decoder, demultiplexer; inverting
74HCT138D		N/a	2098	avai	74HC/HCT138; 3-to-8 line decoder/demultiplexer; inverting
74HCT138PW		N/a	2200	avai	74HC/HCT138; 3-to-8 line decoder/demultiplexer; inverting
74HCT138PW	NXP	N/a	13368	avai	74HC/HCT138; 3-to-8 line decoder/demultiplexer; inverting