74HC125 ,3-stateMAXIMUM RATINGSÎÎSymbol Parameter Value UnitThis device contains protectioncircuitry to guard again ..
74HC125D ,74HC/HCT125; Quad buffer/line driver; 3-statePin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.FUNCTION TABLEINPUTS OUTPUTnOE nA n ..
74HC125DB ,Quad buffer/line driver; 3-stateFEATURES• Output capability: bus driver• I category: MSICC
74HC125DB ,Quad buffer/line driver; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC125DB ,Quad buffer/line driver; 3-stateFunctional description [1]Table 3. Function tableControl Input OutputnOE nA nYLLLHHHX Z[1] H = HIGH ..
74HC125N ,Quad buffer/line driver; 3-statePin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.FUNCTION TABLEINPUTS OUTPUTnOE nA n ..
74LV07A , HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS
74LV08 ,Quad 2-input AND gate
74LV08D ,Quad 2-input AND gateLogic diagram (one gate)5. Pinning information5.1 Pinning74LV0874LV081 141A VCC1B 2 13 4B1A 1 14 VC ..
74LV08D ,Quad 2-input AND gateapplications: 1.0 to 3.6 VThe 74LV08 provides the 2-input AND function.• Accepts TTL input levels b ..
74LV08D ,Quad 2-input AND gateapplications: 1.0 to 3.6 VThe 74LV08 provides the 2-input AND function.• Accepts TTL input levels b ..
74LV08N ,Quad 2-input AND gateFEATURES DESCRIPTIONThe 74LV08 is a low-voltage Si-gate CMOS device and is pin and• Wide operating ..
74HC125
3-state
74HC125
Quad 3−State Noninverting
Buffers
High−Performance Silicon−Gate CMOSThe 74HC125 is identical in pinout to the LS125. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC125 noninverting buffer is designed to be used with 3−state
memory address drivers, clock drivers, and other bus−oriented
systems. The device has four separate output enables that are
active−low.
Features Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 �A High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7A Requirements ESD Performance: HBM � 2000 V; Machine Model � 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates These are Pb−Free Devices
