74HCT123D ,Dual retriggerable monostable multivibrator with resetINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT123N ,Dual retriggerable monostable multivibrator with resetINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT123N. ,Dual retriggerable monostable multivibrator with resetINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT123PW ,Dual retriggerable monostable multivibrator with resetINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT123PW ,Dual retriggerable monostable multivibrator with reset 74HC123; 74HCT123Dual retriggerable monostable multivibrator with resetRev. 8 — 16 December 2011 P ..
74HCT125D ,74HC/HCT125; Quad buffer/line driver; 3-statePin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.FUNCTION TABLEINPUTS OUTPUTnOE nA n ..
74VHC02M ,Quad 2-Input NOR GateFeaturesThe VHC02 is an advanced high-speed CMOS 2-Input
74HC123D-74HC123DB-74HCT123D-74HCT123N-74HCT123N.-74HCT123PW
Dual retriggerable monostable multivibrator with reset
Philips Semiconductors Product specification
Dual retriggerable monostable
multivibrator with reset 74HC/HCT123
FEATURES DC triggered from active HIGH or
active LOW inputs Retriggerable for very long pulses
up to 100% duty factor Direct reset terminates output
pulse Schmitt-trigger action on all inputs
except for the reset input Output capability: standard (except
for nREXT/CEXT) ICC category: MSI
GENERAL DESCRIPTIONThe 74HC/HCT123 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT123 are dual
retriggerable monostable
multivibrators with output pulse width
control by three methods. The basic
pulse time is programmed by
selection of an external resistor
(REXT) and capacitor (CEXT). The
external resistor and capacitor are
normally connected as shown in
Fig.6.
Once triggered, the basic output
pulse width may be extended by
retriggering the gated active
LOW-going edge input (nA) or the
active HIGH-going edge input (nB).
By repeating this process, the output
pulse period (nQ= HIGH, nQ= LOW)
can be made as long as desired.
Alternatively an output delay can be
terminated at any time by a
LOW-going edge on input nRD, which
also inhibits the triggering.
An internal connection from nRD to
the input gates makes it possible to
trigger the circuit by a positive-going
signal at input nRD as shown in the
function table. Figures 7 and 8
illustrate pulse control by retriggering
and early reset. The basic output
pulse width is essentially determined
by the values of the external timing
components REXT and CEXT. For
pulse widths, when CEXT< 10 000 pF,
see Fig.9.
When CEXT > 10 000 pF, the typical
output pulse width is defined as:= 0.45× REXT× CEXT (typ.),
where: = pulse width in ns;
REXT= external resistor in kΩ;
CEXT= external capacitor in pF.
Schmitt-trigger action in the nA and
nB inputs, makes the circuit highly
tolerant to slower input rise and fall
times.
The ‘123’ is identical to the ‘423’ but
can be triggered via the reset input.
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C; tr =tf =6ns
Notes CPD is used to determine the dynamic power dissipation (PD in μW): =CPD× VCC2×fi+ ∑(CL× VCC2×fo)+ 0.75× CEXT VCC2×fo+D×16× VCC where:= input frequency in MHz= output frequency in MHz= duty factor in %= output load capacitance in pF
VCC= supply voltage in V
CEXT= timing capacitance in pF (CL× VCC2×fo) sum of outputs For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC− 1.5V
Philips Semiconductors Product specification
Dual retriggerable monostable
multivibrator with reset 74HC/HCT123
ORDERING INFORMATION
PIN DESCRIPTION
Philips Semiconductors Product specification
Dual retriggerable monostable
multivibrator with reset 74HC/HCT123
FUNCTION TABLE
Note If the monostable was triggered
before this condition was
established, the pulse will
continue as programmed. = HIGH voltage level = LOW voltage level = don’t care = LOW-to-HIGH transition = HIGH-to-LOW transition
= one HIGH level output pulse
= one LOW level output pulse
Philips Semiconductors Product specification
Dual retriggerable monostable
multivibrator with reset 74HC/HCT123
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard (except for nREXT/CEXT)
ICC category: MSI
Philips Semiconductors Product specification
Dual retriggerable monostable
multivibrator with reset 74HC/HCT123
AC CHARACTERISTICS FOR 74HCGND=0 V; tr =tf=6 ns; CL =50pF
Philips Semiconductors Product specification
Dual retriggerable monostable
multivibrator with reset 74HC/HCT123
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard (except for nREXT / CEXT)
ICC category: MSI
Note to HCT typesThe value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
Philips Semiconductors Product specification
Dual retriggerable monostable
multivibrator with reset 74HC/HCT123
AC CHARACTERISTICS FOR 74HCTGND=0 V; tr =tf=6 ns; CL =50pF
Philips Semiconductors Product specification
Dual retriggerable monostable
multivibrator with reset 74HC/HCT123
Notes to AC characteristics For other REXT and CEXT combinations see Fig.9.
If CEXT>10 nF, the next formula is valid: =K× REXT× CEXT (typ.)
where: tW = output pulse width in ns;
REXT= external resistor in kΩ; CEXT= external capacitor in pF; = constant = 0.55 for VCC= 5.0 V and 0.48 for VCC= 2.0V.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT / CEXT) is approximately 7 pF. The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT.
The output pulse width will only be extended when the time between the active-going edges of the trigger input pulses
meets the minimum retrigger time.
If CEXT>10 pF, the next formula (at VCC= 5.0 V) for the set-up time of a retrigger pulse is valid:
trt= 30 + 0.19× REXT× CEXT0.9 +13× REXT1.05 (typ.)
where: trt = retrigger time in ns;
CEXT= external capacitor in pF;
REXT= external resistor in kΩ.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT / CEXT) is 7 pF. When the device is powered-up, initiate the device via a reset pulse, when CEXT<50 pF.