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74HC109D
Dual JK flip-flop with set and reset; positive-edge trigger
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
FEATURESJ,K inputs for easy D-type flip-flop Toggle flip-flop or “do nothing” mode Output capability: standard ICC category: flip-flops
GENERAL DESCRIPTIONThe 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
(SD) and reset (RD) inputs; also complementary Q andQ
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J andK inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J andK inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes CPD is used to determine the dynamic power dissipation (PDin μW): = CPD× VCC2×fi +∑ (CL× VCC2×fo) where: = input frequency in MHz = output frequency in MHz (CL× VCC2×fo) = sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC− 1.5V.
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
PIN DESCRIPTION
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
FUNCTION TABLE
Notes H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time
prior to the LOW-to-HIGH CP transition
X = don’t care = LOW-to-HIGH CP transition
PACKAGE OUTLINESSee “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HCGND = 0 V; tr = tf = 6 ns; CL = 50 pF
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HCTGND = 0 V; tr = tf = 6 ns; CL = 50 pF
