74HC107N ,Dual JK flip-flop with reset; negative-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC107N ,Dual JK flip-flop with reset; negative-edge triggerGENERAL DESCRIPTIONoperation.The 74HC/HCT107 are high-speed Si-gate CMOS devicesThe reset (nR) is a ..
74HC107N ,Dual JK flip-flop with reset; negative-edge triggerFEATURES The 74HC/HCT107 are dual negative-edge triggeredJK-type flip-flops featuring individual J, ..
74HC107N ,Dual JK flip-flop with reset; negative-edge trigger
74HC109D ,Dual JK flip-flop with set and reset; positive-edge triggerGENERAL DESCRIPTIONthe LOW-to-HIGH clock transition for predictableThe 74HC/HCT109 are high-speed S ..
74HC109D ,Dual JK flip-flop with set and reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74LS74 ,Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary OutputsFeaturesof the rising edge of the clock. The data on the D input mayYAlternate military/aerospace d ..
74LS74 ,Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs54LS74/DM54LS74A/DM74LS74ADualPositive-Edge-TriggeredDFlip-FlopswithPreset,ClearandComplementaryOut ..
74LS75 ,Quad LatchSN54/74LS754-BIT D LATCHSN54/74LS77The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem- ..
74LS76 ,Dual J-K Flip-Flop(with Preset and Clear)
74LS76 ,Dual J-K Flip-Flop(with Preset and Clear)
74LS90 ,Decade and Binary CountersLOGIC DIAGRAM CONNECTION DIAGRAMDIP (TOP VIEW)LS921 14CP CP1 02 13NCNCJ Q J Q J Q J Q143 12NC Q0CPC ..
74HC107N
Dual JK flip-flop with reset; negative-edge trigger
