74HC107D ,Dual JK flip-flop with reset; negative-edge triggerGENERAL DESCRIPTIONoperation.The 74HC/HCT107 are high-speed Si-gate CMOS devicesThe reset (nR) is a ..
74HC107N ,Dual JK flip-flop with reset; negative-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC107N ,Dual JK flip-flop with reset; negative-edge triggerGENERAL DESCRIPTIONoperation.The 74HC/HCT107 are high-speed Si-gate CMOS devicesThe reset (nR) is a ..
74HC107N ,Dual JK flip-flop with reset; negative-edge triggerFEATURES The 74HC/HCT107 are dual negative-edge triggeredJK-type flip-flops featuring individual J, ..
74HC107N ,Dual JK flip-flop with reset; negative-edge trigger
74HC109D ,Dual JK flip-flop with set and reset; positive-edge triggerGENERAL DESCRIPTIONthe LOW-to-HIGH clock transition for predictableThe 74HC/HCT109 are high-speed S ..
74LS74 ,Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs54LS74/DM54LS74A/DM74LS74ADualPositive-Edge-TriggeredDFlip-FlopswithPreset,ClearandComplementaryOut ..
74LS74 ,Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary OutputsFeaturesof the rising edge of the clock. The data on the D input mayYAlternate military/aerospace d ..
74LS74 ,Dual Positive-Edge-Triggered D Flip-Flops with Preset/ Clear and Complementary Outputs54LS74/DM54LS74A/DM74LS74ADualPositive-Edge-TriggeredDFlip-FlopswithPreset,ClearandComplementaryOut ..
74LS75 ,Quad LatchSN54/74LS754-BIT D LATCHSN54/74LS77The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem- ..
74LS76 ,Dual J-K Flip-Flop(with Preset and Clear)
74LS76 ,Dual J-K Flip-Flop(with Preset and Clear)
74HC107D-74HC107N-74HCT107D
74HC/HCT107; Dual JK flip-flop with reset; negative-edge trigger
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
FEATURES Output capability: standard ICC category: flip-flops
GENERAL DESCRIPTIONThe 74HC/HCT107 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT107 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and theQ output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATAGND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes CPD is used to determine the dynamic power dissipation (PDin μW): = CPD× VCC2×fi +∑ (CL× VCC2×fo) where: = input frequency in MHz = output frequency in MHz (CL× VCC2×fo) = sum of outputs= output load capacitance in pF
VCC= supply voltage in V For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC− 1.5V.
ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
PIN DESCRIPTION
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
FUNCTION TABLE
Note H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP
transition
X = don’t care = HIGH-to-LOW CP transition
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HCGND = 0 V; tr = tf = 6 ns; CL = 50 pF
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT107
DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: flip-flops
Note to HCT typesThe value of additional quiescent supply current (ΔICC) for a unit load of 1 is given in the family specifications.
To determine ΔICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCTGND = 0 V; tf = tf = 6 ns; CL = 50 pF
