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74GTL1655
16 BIT LVTTL TO GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION
1/14December 2001 HIGH SPEED GTL/GTL+ UNIVERSAL
TRANSCEIVER :
tPD = 4.6 ns (MAX.) A to B at VCC = 3V COMBINES D-TYPE LATCHES AND D-TYPE
FLIP-FLOPS FOR OPERATION IN
TRANSPARENT, LATCHED, OR CLOCKED
MODE
� OPERATING VOLTAGE RANGE:
VCC(OPR) = 3.0V to 3.6V
� SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL=24mA (MIN) at VCC = 3V (A PORT)
� OUTPUT IMPEDANCE:OL = 100mA (MIN) at VCC = 3V (B PORT) HIGH-IMPEDANCE STATE DURING POWER
UP AND POWER DOWN up to Vcc=1.5V
PERMITT LIVE INSERTION B-PORT PRECHARGED BY BIASVcc
REDUCE NOISE ON THE LINE DURING
LIVE INSERTION EDGE RATE-CONTROL INPUT
CONFIGURES THE B-PORT OUTPUT RISE
AND FALL TIMES BUS HOLD ON DATA INPUTS ELIMINATES
THE NEED FOR EXTERNAL PULL-UP/
PULL-DOWN RESISTORS (A PORT) DISTRIBUTED VCC AND GND PIN
CONFIGURATION MINIMIZES HIGH-SPEED
SWITCHING NOISE IN PARALLEL
COMUNICATIONS .
� PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 1655
DESCRIPTIONThe 74GTL1655 devices are 16-bit high-drive
(100mA), low-output-impedance universal bus
transceivers designed for backplane applications.
The 74GTL1655 devices provide live-insertion
capability for backplane applications by tolerating
active signals on the data ports when the devices
are powered off. In addition, a biasing pin
preconditions the GTL/GTL+ port to minimize
disruption to an active backplane.
The edge rate-control (V ERC ) input is provided so
the rise and fall time of the B outputs can be
configured to optimize for various backplane
loading conditions. Data flow in each direction is
controlled by output-enable (OEAB and OEBA),
74GTL165516 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS
TRANSCEIVERS WITH LIVE INSERTION
ORDER CODES
PIN CONNECTION
74GTL16552/14
latch-enable (LEAB and LEBA), and clock (CLK)
inputs. For A-to-B data flow, the devices operate
in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLK is held at
a high or low logic level. If LEAB is low, the A data
is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OEAB is low, the outputs
are active. When OEAB is high, the outputs are in
the high-impedance state. Data flow for B to A is
similar to that of A to B, but uses OEBA, LEBA,
and CLK. The output enable (OE) is used to
disable both ports simultaneously.
Active bus-hold circuitry is provided on the A port
to hold unused or floating data inputs at a valid
logic level. When VCC is between 0 and 1.5 V, the
device is in the high-impedance state during
power up or power down. However, to ensure the
high-impedance state above 1.5V , OE should be
tied to VCC through a pullup resistor; the minimum
value of the resistor is determined by the
current-sinking capability of the driver.
All input and output are equipped with protection
circuits against static discharge, giving them 2KV
ESD immunity and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
74GTL16553/14
FUNCTION TABLE (1) 1) A to B data flow is shown. B to A flow is similar, but uses OEBA, LEBA and CLK
2) Output level before the indicated steady-state input conditions were established, provided that CLK was high before LEAB went low
3) Output level before the indicated steady-state input conditions were established
OUTPUT ENABLE TRUTH TABLE
B-PORT EDGE RATE CONTROL (VERC) TRUTH TABLE
74GTL16554/14
LOGIC DIAGRAM
74GTL16555/14
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not
implied
RECOMMENDED OPERATING CONDITIONS 1) VTT and RTT can be adjusted to adapt backplane impedance if DC raccomanded IOL ratings are not exceeded
2) VREF can be adjusted to optimaze noise margin (typ two-thirds VTT)
74GTL16556/14
DC SPECIFICATIONS (*) For I/O ports, the parameter IOZ includes the input leakage current
74GTL16557/14
LIVE INSERTION SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS for GTL (VCC=3.3 ± 0.3V, VTT=1.2V, VREF=0.8V, VERC=VCC or GND)
