74FCT16652CTPVCTG4 ,16-Bit Bus Transceivers and Registers with 3-State Outputs 56-SSOP -40 to 85Block DiagramsOEAB1 OEAB2OEBA OEBA1 2CLKBA1CLKBA2SBASBA 21CLKABCLKAB 21SAB SAB2 B REG1 B REGD DC CA ..
74FCT240 ,Inverting Octal Buffer/Line Driver with TRI-STATE Outputsfeatures GTO output control and undershoot I 64 mA (commercial), 48 mA (military)OLcorrector in add ..
74FCT240 ,Inverting Octal Buffer/Line Driver with TRI-STATE OutputsFeaturesYI and I reduced to 40.0 mA andg2.5 mAThe ’FCT240 is an inverting octal buffer and line dri ..
74FCT244 , FCT Interface Logic Octal Buffers/Line Drivers, Three-State
74FCT244 , FCT Interface Logic Octal Buffers/Line Drivers, Three-State
74FCT244 , FCT Interface Logic Octal Buffers/Line Drivers, Three-State
74LS139 ,Decoder/DemultiplexerSN54/74LS139DUAL 1-OF-4 DECODER/DEMULTIPLEXERThe LSTTL/MSI SN54/74LS139 is a high speed Dual 1-of-4 ..
74LS14 ,Hex Inverter with Schmitt Trigger Inputsorder data line is encoded. Both devices have data inputs and outputswhich are active at the low lo ..
74LS148 ,8-line-to-3-line Octal Priority Encoders
74LS148 ,8-line-to-3-line Octal Priority Encoders
74LS15 ,TRIPLE 3-INPUT AND GATE
74LS15 ,TRIPLE 3-INPUT AND GATE
74FCT16652CTPVCTG4-CY74FCT16652CTPVC
16-Bit Bus Transceivers and Registers with 3-State Outputs 56-SSOP -40 to 85
1CY74FCT162652T
Featuresoff supports partial-power-down mode operation Edge-rate control circuitry for significantly improved
noise characteristics Typical output skew < 250 ps ESD > 2000V TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages Industrial temperature range of −40˚C to +85˚C
CC = 5V ± 10%
CY74FCT16652T Features:
64 mA sink current, 32 mA source current Typical V OLP (ground bounce) <1.0V at VCC = 5V,A = 25˚CCY74FCT162652T Features:
Balanced 24 mA output drivers Reduced system switching noise Typical V OLP (ground bounce) <0.6V at VCC = 5V,A = 25˚C
Functional DescriptionThese 16-bit, high-speed, low-power, registered transceivers
that are organizedas two independent 8-bit bus transceivers
withthree-state D-type registers and control circuitry arranged
for multiplexed transmissionof data directly fromthe input bus
orfrom theinternal storage registers. OEAB and OEBAcontrol
pins are provided tocontrol the transceiver functions. SABand
SBA control pins are providedto select either real-timeor
stored data transfer.
Dataon theAorB data bus,or both, canbe storedin the
internalD flip-flops by LOW-to-HIGH transitionsat the
appropriate clock pins (CLKABor CLKBA), regardlessof the
selector enable control pins. When SAB and SBA arein the
real-timetransfermode,itis alsopossibleto store data without
using the internal D-type flip-flopsby simultaneously enabling
OEAB and OEBA.In this configuration, each output reinforces
its input. Thus, whenall other data sourcesto the two setsof
bus lines areat high impedance, each setof bus lines will
remain at its last state.
This device is fully specified for partial-power-down
applications usingIoff. TheIoff circuitry disables the outputs,
preventing damaging current backflow through the device
when it is powered down.
The CY74FCT16652T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162652T has 24-mA balanced output drivers
with current-limiting resistorsin the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162652T is ideal for driving transmission lines.
TO7 OTHER CHANNELS
1OEAB
1A1
1OEBA
1CLKBA
1CLKAB
1SBA
1B1
1SAB
FCT16652-1
2OEAB
2SAB
2OEBA
2CLKBA
2CLKAB
2SBA
2B1
2A17 OTHER CHANNELS FCT16652-2
Logic Block Diagrams
