74F899 ,9-Bit Latchable Transceiver with Parity Generator/Checkerapplications in place of the74F657 and 74F373 (no need to change T/R to checkparity) Ordering Code: ..
74f899 ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899QC ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899QCX ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899QCX ,9-Bit Latchable Transceiver with Parity Generator/CheckerFunctional DescriptionThe 74F899 has three principal modes of operation which • Bus A (B) communica ..
74F899SC ,9-Bit Latchable Transceiver with Parity Generator/CheckerFeaturesThe 74F899 is a 9-bit to 9-bit parity transceiver with trans- Latchable transceiver with o ..
74LS05 ,Hex Inverters with Open-Collector OutputsHEX INVERTER
DESCRIPTION
The T54LS05/T74LS05 is a high speed HEX IN.
VERTER fabricated in LOW PO ..
74LS08 ,Quad 2-Input AND GatesDM74LS08 Quad 2-Input AND GatesAugust 1986Revised March 2000DM74LS08Quad 2-Input AND Gates
74LS09 ,Quad 2-Input AND Gates with Open-Collector OutputsGeneral Description Pull-Up Resistor EquationsThis device contains four independent gates each of w ..
74LS10 ,Triple 3-Input NAND GateGeneral DescriptionThis device contains three independent gates each ofwhich performs the logic NAN ..
74LS11 ,Triple 3-Input AND GateGeneral DescriptionThis device contains three independent gates each ofwhich performs the logic AND ..
74LS112 ,Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary OutputsSN54/74LS112ADUAL JK NEGATIVEEDGE-TRIGGERED FLIP-FLOPThe SN54/74LS112A dual JK flip-flop
74F899
9-Bit Latchable Transceiver with Parity Generator/Checker
74F899 9-Bit Latchable Transceiver February 1989 Revised August 1999 74F899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description Features The 74F899 is a 9-bit to 9-bit parity transceiver with trans- � Latchable transceiver with output sink of 24 mA at the parent latches. The device can operate as a feed-through A-bus and 64 mA at the B-bus transceiver or it can generate/check parity from the 8-bit � Option to select generate parity and check or data busses in either direction. It has a guaranteed current “feed-through” data/parity in directions A-to-B or B-to-A sinking capability of 24 mA at the A-bus and 64 mA at the � Independent latch enables for A-to-B and B-to-A B-bus. directions The 74F899 features independent latch enables for the � Select pin for ODD/EVEN parity A-to-B direction and the B-to-A direction, a select pin for � ERRA and ERRB output pins for parity checking ODD/EVEN parity, and separate error signal output pins for checking parity. � Ability to simultaneously generate and check parity � May be used in systems applications in place of the 74F543 and 74F280 � May be used in system applications in place of the 74F657 and 74F373 (no need to change T/R to check parity) Ordering Code: Order Number Package Number Package Description 74F899SC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F899QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for SOIC Pin Assignment for PCC Logic Symbol © 1999 DS010195
