74F74SJ ,Dual D-Type Positive Edge-Triggered Flip-FlopGeneral Descriptioninput.The F74 is a dual D-type flip-flop with Direct Clear and SetAsynchronous I ..
74F74SJX ,Dual D-Type Positive Edge-Triggered Flip-FlopGeneral Descriptioninput.The F74 is a dual D-type flip-flop with Direct Clear and SetAsynchronous I ..
74F779PC ,8-Bit Bidirectional Binary Counter with 3-STATE OutputsFeaturesThe 74F779 is a fully synchronous 8-stage up/down
74F74PC-74F74SC-74F74SCX-74F74SJ-74F74SJX
Dual D-Type Positive Edge-Triggered Flip-Flop
74F74 Dual D-Type Positive Edge-Triggered Flip-Flop April 1988 Revised September 2000 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop the outputs until the next rising edge of the Clock Pulse General Description input. The F74 is a dual D-type flip-flop with Direct Clear and Set Asynchronous Inputs: inputs and complementary (Q, Q) outputs. Information at LOW input to S sets Q to HIGH level the input is transferred to the outputs on the positive edge D of the clock pulse. Clock triggering occurs at a voltage level LOW input to C sets Q to LOW level D of the clock pulse and is not directly related to the transition Clear and Set are independent of clock time of the positive-going pulse. After the Clock Pulse input Simultaneous LOW on C and S threshold voltage has been passed, the Data input is D D locked out and information present will not be transferred to makes both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 DS009469
