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74F652SCFAIRCHILN/a5avaiTransceivers/Registers
74F652SCXFAIN/a217avaiTransceivers/Registers
74F652SPCFAIRCHILDN/a19avaiTransceivers/Registers
74F652SPCFAIN/a44avaiTransceivers/Registers
74F652SPCFSCN/a45avaiTransceivers/Registers


74F652SCX ,Transceivers/RegistersFeaturesThese devices consist of bus transceiver circuits with

74F652SC-74F652SCX-74F652SPC
Transceivers/Registers
74F652 Transceivers/Registers March 1988 Revised January 2004 74F652 Transceivers/Registers General Description Features These devices consist of bus transceiver circuits withIndependent registers for A and B buses D-type flip-flops, and control circuitry arranged for multi-Multiplexed real-time and stored data plexed transmission of data directly from the input bus or 74F652 non-inverting data path from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. Ordering Code: Order Number Package Number Package Description 74F652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide (Note 1) 74F652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2004 DS009581
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