74F652 ,Transceivers/RegistersFeaturesThese devices consist of bus transceiver circuits with
74F652
Transceivers/Registers
74F651 • 74F652 Transceivers/Registers March 1988 Revised October 2000 74F651 74F652 Transceivers/Registers General Description Features These devices consist of bus transceiver circuits withIndependent registers for A and B buses D-type flip-flops, and control circuitry arranged for multi-Multiplexed real-time and stored data plexed transmission of data directly from the input bus or Choice of non-inverting and inverting data paths from internal registers. Data on the A or B bus will be 74F651 inverting clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are 74F652 non-inverting provided to control the transceiver function. Ordering Code: Order Number Package Number Package Description 74F651SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F651SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74F652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 DS009581
