74F64PC ,4-2-3-2-Input AND-OR-Invert GateGeneral DescriptionThis device contains gates configured to perform a 4-2-3-2input AND-OR-INVERT fu ..
74F651 ,Transceivers/Registers54F/74F651 54F/74F652Transceivers/Registers#December199454F/74F651 54F/74F652#Transceivers/Register ..
74F651SC ,Transceivers/Registers54F/74F651 54F/74F652Transceivers/Registers#December199454F/74F651 54F/74F652#Transceivers/Register ..
74F651SPC ,Transceivers/RegistersFeaturesThese devices consist of bus transceiver circuits with D- Independent registers for A and ..
74F652 ,Transceivers/RegistersFeaturesThese devices consist of bus transceiver circuits with
74F64PC
4-2-3-2-Input AND-OR-Invert Gate
74F64 4-2-3-2-Input AND-OR-Invert Gate April 1988 Revised March 1999 74F64 4-2-3-2-Input AND-OR-Invert Gate General Description This device contains gates configured to perform a 4-2-3-2 input AND-OR-INVERT function. Ordering Code: Order Number Package Number Package Description 74F64SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F64SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F64PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Unit Loading/Fan Out Input I /I U.L. IH IL Pin Names Description HIGH/LOW Output I /I OH OL A , B , C , D Inputs 1.0/1.0 20 μA/−0.6 mA n n n n O Output 50/33.3 −1 mA/20 mA © 1999 DS009467.prf
