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74F623
Inverting Octal Bus Transceiver with TRI-STATE Outputs
TL/F/9577
74F620
74F623
Inverting
Octal
Bus
Transceiver
with
TRI-STATE
Outputs
August 1995
74F620# 74F623
Inverting Octal Bus Transceiver with TRI-STATEÉ
Outputs
General Description
Thesedevicesare octalbus transceivers designedfor asyn-
chronous two-way data flow betweentheAandB busses.
Both bussesare capableof sinking64mAand have TRI-
STATE outputs. Dual enable pins (GAB, GBA) allow data
transmission fromtheAbustotheBbusor fromtheBbustheA bus.The ’F620isan inverting optionofthe ’F623.
Features Designedfor asynchronous two-way data flow between
busses Outputs sink64mA Dual enable inputs control directionof data flow Guaranteed 4000V minimum ESD protection ’F620isan inverting optionofthe ’F623
Commercial Package PackageDescriptionNumber
74F620PC N20A 20-Lead (0.300× Wide) Molded Dual-In-Line
74F623PC N20A 20-Lead (0.300× Wide) Molded Dual-In-Line
74F623SC (Note1) M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC
Note1: Devicesalso availablein13×reel.UsesuffixeSCX.
Logic Symbol
TL/F/9577–3
Unit Loading/Fan Out
74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
GBA, GAB EnableInputs 1.0/1.0 20 mA/b0.6mA
A0–A7 AInputsor 3.5/1.083 70 mA/b0.4mA
TRI-STATEOutputs 150/40 b3mA/64mA
B0–B7 BInputsor 3.5/1.083 70 mA/b0.4mA
TRI-STATEOutputs 150/40 b3mA/64mA
Connection Diagram
PinAssignmentfor
DIP, SOIC
TL/F/9577–1
FASTÉand TRI-STATEÉareregistered trademarks ofNationalSemiconductor Corporation
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
