74F569PC ,4-Bit Bidirectional Counter with 3-STATE OutputsFunctional DescriptionThe 74F569 counts in the modulo-16 binary sequence. stage counters, the conne ..
74F569SJ ,4-Bit Bidirectional Counter with 3-STATE OutputsFunctional DescriptionThe 74F569 counts in the modulo-16 binary sequence. stage counters, the conne ..
74F569SJ ,4-Bit Bidirectional Counter with 3-STATE OutputsFeaturesThe 74F569 is a fully synchronous, reversible counter with Synchronous counting and loadin ..
74F573 ,Octal D-Type Flip-Flop with 3-STATE OutputsFunctional Description Function TableThe 74F573 contains eight D-type latches with 3-state out-Inpu ..
74F573. ,Octal D-Type Flip-Flop with 3-STATE Outputs54F/74F573OctalD-TypeLatchwithTRI-STATEOutputsAugust199554F/74F573OctalD-TypeLatchwithTRI-STATEÉOut ..
74F573PC ,Octal D-Type Latch with TRI-STATE OutputsFunctional Description Function TableThe 74F573 contains eight D-type latches with 3-state out-Inpu ..
74LCX245 ,LOW-VOLTAGE CMOS OCTAL TRANSCEIVERTC74LCX245F/FW/FTTC74LCX245F, TC74LCX245FW, TC74LCX245FTWITH 5V TOLERANT INPUTS AND OUTPUTSThe TC74 ..
74LCX245BQX ,Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and OutputsFeaturesThe LCX245 contains eight non-inverting bidirectional buff-
74F569PC-74F569SJ
4-Bit Bidirectional Counter with 3-STATE Outputs
74F569 4-Bit Bidirectional Counter with 3-STATE Outputs April 1988 Revised August 1999 74F569 4-Bit Bidirectional Counter with 3-STATE Outputs General Description Features The 74F569 is a fully synchronous, reversible counter with � Synchronous counting and loading 3-STATE outputs. The 74F569 is a binary counter, featur- � Lookahead carry capability for easy cascading ing preset capability for programmable operation, carry loo- � Preset capability for programmable operation kahead for easy cascading, and a U/D input to control the � 3-STATE outputs for bus organized systems direction of counting. For maximum flexibility there are both synchronous and master asynchronous reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) out- puts. All state changes except Master Reset are initiated by the rising edge of the clock. A HIGH signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading. Ordering Code: Order Number Package Number Package Description 74F569SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F569SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F569PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC FAST is a registered trademark of . © 1999 DS009565
