74F538 ,1-of-8 Decoder with 3-STATE Outputs74F538 1-of-8 Decoder with 3-STATE OutputsApril 1988Revised October 200074F5381-of-8 Decoder with 3 ..
74F538PC ,1-of-8 Decoder with 3-STATE Outputs74F538 1-of-8 Decoder with 3-STATE OutputsApril 1988Revised January 200474F5381-of-8 Decoder with 3 ..
74F538SCX ,1-of-8 Decoder with 3-STATE Outputs74F538 1-of-8 Decoder with 3-STATE OutputsApril 1988Revised January 200474F5381-of-8 Decoder with 3 ..
74F539 ,Octal D-Type Flip-Flop with 3-STATE OutputsGeneral DescriptionThe 74F539 contains two independent decoders. Eachaccepts two Address (A , A ) i ..
74F539PC ,Dual 1-of-4 Decoder with 3-STATE OutputsGeneral DescriptionThe 74F539 contains two independent decoders. Eachaccepts two Address (A , A ) i ..
74F539SC ,Dual 1-of-4 Decoder with 3-STATE OutputsGeneral DescriptionThe 74F539 contains two independent decoders. Eachaccepts two Address (A , A ) i ..
74LCX16374G ,Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputsapplications. The device is byte controlled. A buff-
74F538
1-of-8 Decoder with 3-STATE Outputs
74F538 1-of-8 Decoder with 3-STATE Outputs April 1988 Revised October 2000 74F538 1-of-8 Decoder with 3-STATE Outputs General Description Features The 74F538 decoder/demultiplexer accepts three AddressOutput polarity control (A –A ) input signals and decodes them to select one of 0 2Data demultiplexing capability eight mutually exclusive outputs. A polarity control input (P) Multiple enables for expansion determines whether the outputs are active LOW or active 3-STATE outputs HIGH. A HIGH Signal on either of the active LOW Output Enable (OE) inputs forces all outputs to the high imped- ance state. Two active HIGH and two active LOW input enables are available for easy expansion to 1-of 32 decod- ing with four packages, or for data demultiplexing to 1-of-8 or 1-of-16 destinations. Ordering Code: Order Number Package Number Package Description 74F538SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F538SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F538PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 DS009551
