74F533SJ ,Octal Transparent Latch with TRI-STATE OutputsFeaturesThe 74F533 consists of eight latches with 3-STATE outputs
74F533SJ
Octal Transparent Latch with TRI-STATE Outputs
TL/F/9548
54F/74F533
Octal
Transparent
Latch
with
TRI-STATE
Outputs
May 1995
54F/74F533
Octal Transparent Latch with TRI-STATEÉ Outputs
General Description
The ’F533 consistsof eight latcheswith TRI-STATEoutputs
forbus organized system applications.The flip-flops appear
transparenttothe data when Latch Enable (LE)is HIGH.
WhenLEis LOW,the data that meetsthe setup timesis
latched. Data appearsonthebus whenthe Output Enable
(OE)is LOW. When OEis HIGHthebus outputisinthe high
impedance state. The ’F533isthe sameasthe ’F373,ex-
ceptthatthe outputsare inverted.
Features Eight latchesina single package TRI-STATE outputsforbus interfacing Inverted versionofthe ’F373 Guaranteed 4000V minimum ESD protection
Commercial Military Package Package DescriptionNumber
74F533PC N20A 20-Lead (0.300× Wide) Molded Dual-In-Line
54F533DM (Note2) J20A 20-Lead CeramicDual-In-Line
74F533SC (Note1) M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC
74F533SJ (Note1) M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ
54F533FM(Note2) W20A 20-Lead Cerpack
54F533LM (Note2) E20A 20-Lead CeramicLeadless Chip Carrier,TypeC
Note 1:Devicesalso availablein13×reel. UsesuffixeSCXandSJX.
Note 2:Militarygrade devicewith environmentaland burn-in processing.Use suffixe DMQB, FMQBandLMQB.
Logic Symbols Connection Diagrams
IEEE/IEC
TL/F/9548–4
TL/F/9548–1
Pin Assignment
for DIP, SOICand Flatpak
TL/F/9548–2
Pin Assignment
for LCC
TL/F/9548–3
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
