74F433SPC ,First-In First-Out (FIFO) Buffer Memoryapplications. It is organized as 64-words by 4-bits 3-STATE outputsand may be expanded to any numbe ..
74F51 ,Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate
74F51 ,Dual 2-wide 2-input, 2-wise 3-input AND-OR-invert gate
74F51PC ,Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert GateElectrical CharacteristicsSymbol Parameter Min Typ Max Units V ConditionsCCV Input HIGH Voltage 2.0 ..
74F51PC ,Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert GateGeneral DescriptionThis device contains two independent logic units, one per-forming a 2-2 AND-OR-I ..
74F521 ,8-Bit Identity ComparatorFeaturesThe 74F521 is an expandable 8-bit comparator. It com-
74F433SPC
First-In First-Out (FIFO) Buffer Memory
74F433 First-In First-Out (FIFO) Buffer Memory April 1988 Revised August 1999 74F433 First-In First-Out (FIFO) Buffer Memory General Description Features The 74F433 is an expandable fall-through type high-speed � Serial or parallel input First-In First-Out (FIFO) Buffer Memory that is optimized for � Serial or parallel output high-speed disk or tape controller and communication � Expandable without additional logic buffer applications. It is organized as 64-words by 4-bits � 3-STATE outputs and may be expanded to any number of words or any num- ber of bits in multiples of four. Data may be entered or � Fully compatible with all TTL families extracted asynchronously in serial or parallel, allowing eco- � Slim 24-pin package nomical implementation of buffer memories. � 9423 replacement The 74F433 has 3-STATE outputs that provide added ver- satility, and is fully compatible with all TTL families. Ordering Code: Order Number Package Number Package Description 74F433SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Logic Symbol Connection Diagram © 1999 DS009544
