74F399SJX ,Quad 2-Port Register74F399 Quad 2-Port RegisterApril 1988Revised January 200474F399Quad 2-Port Register
74F399SJX ,Quad 2-Port RegisterFunctional Description Function TableThe 74F399 is a high-speed quad 2-port registers. TheyInputs O ..
74F401 ,CRC Generator/Checker
74F401PC ,CRC Generator/CheckerFunctional DescriptionThe 74F401 is a 16-bit programmable device which oper- transition of the Cloc ..
74F402PC ,Serial Data Polynomial Generator/Checker
74F403ASPC ,First-In First-Out (FIFO) Buffer Memoryapplications. It is organized as 16-words by 4-bits 3-STATE outputsand may be expanded to any numbe ..
74LCX157MTR ,LOW VOLTAGE CMOS QUAD 2 CHANNEL MULTIPLEXER WITH 5V TOLERANT INPUTSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74LCX157MX ,Low Voltage Quad 2-Input Multiplexer with 5V Tolerant InputsFeaturesThe LCX157 is a high-speed quad 2-input multiplexer. Four
74F399PC-74F399SC-74F399SJX
Quad 2-Port Register
74F399 Quad 2-Port Register April 1988 Revised January 2004 74F399 Quad 2-Port Register General Description Features The 74F399 is the logical equivalent of a quad 2-input mul-Select inputs from two data sources tiplexer feeding into four edge-triggered flip-flops. A com-Fully positive edge-triggered operation mon Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flops on the ris- ing edge of the clock. Ordering Code: Order Number Package Number Package Description 74F399SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74F399SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F399PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Unit Loading/Fan Out Input I /I U.L. IH IL Pin Names Description HIGH/LOW Output I /I OH OL S Common Select Input 1.0/1.0 20 μA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 μA/−0.6 mA I –I Data Inputs from Source 0 1.0/1.0 20 μA/−0.6 mA 0a 0d I –I Data Inputs from Source 1 1.0/1.0 20 μA/−0.6 mA 1a 1d Q –Q Register True Outputs 50/33.3 −1 mA/20 mA a d © 2004 DS009533
