74F379 ,Quad Parallel Register with EnableFunctional Description Truth TableThe 74F379 consists of four edge-triggered D-type flip-Inputs Out ..
74F379 ,Quad Parallel Register with Enablefeatures
74F379
Quad Parallel Register with Enable
74F379 Quad Parallel Register with Enable May 1988 Revised October 2000 74F379 Quad Parallel Register with Enable General Description Features The 74F379 is a 4-bit register with buffered commonEdge triggered D-type inputs Enable. This device is similar to the 74F175 but featuresBuffered positive edge-triggered clock the common Enable rather than common Master Reset. Buffered common enable input True and complement outputs Ordering Code: Order Number Package Number Package Description 74F379SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F379SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F379PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 DS009527
