74F377SJ ,Octal D Flip-Flop with Clock Enableapplicationsthe Clock Enable (CE) is LOW.
74F377PC-74F377SC-74F377SCX-74F377SJ-74F377SJX
Octal D-Type Flip-Flop with Clock Enable
74F377 Octal D-Type Flip-Flop with Clock Enable April 1988 Revised September 2000 74F377 Octal D-Type Flip-Flop with Clock Enable General Description Features The 74F377 has eight edge-triggered, D-type flip-flops withIdeal for addressable register applications individual D inputs and Q outputs. The common bufferedClock enable for address and data synchronization Clock (CP) input loads all flip-flops simultaneously, when applications the Clock Enable (CE) is LOW. Eight edge-triggered D-type flip-flops The register is fully edge-triggered. The state of each D Buffered common clock input, one setup time before the LOW-to-HIGH clock transi- See 74F273 for master reset version tion, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior toSee 74F373 for transparent latch version the LOW-to-HIGH clock transition for predictable operation.See 74F374 for 3-STATE version Ordering Code: Order Number Package Number Package Description 74F377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 DS009525
