74F273SJX ,Octal D-Type Flip-Flopapplications where the true output onlyis required and the Clock and Master Reset are common toall ..
74F273SJX ,Octal D-Type Flip-FlopFeaturesThe 74F273 has eight edge-triggered D-type flip-flops with
74F273SJ-74F273SJX
Octal D-Type Flip-Flop
74F273 Octal D-Type Flip-Flop April 1988 Revised September 2000 74F273 Octal D-Type Flip-Flop General Description Features The 74F273 has eight edge-triggered D-type flip-flops withIdeal buffer for MOS microprocessor or memory individual D inputs and Q outputs. The common bufferedEight edge-triggered D-type flip-flops Clock (CP) and Master Reset (MR) inputs load and reset Buffered common clock (clear) all flip-flops simultaneously. Buffered, asynchronous Master Reset The register is fully edge-triggered. The state of each D See 74F377 for clock enable version input, one setup time before the LOW-to-HIGH clock transi- See 74F373 for transparent latch version tion, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock orSee 74F374 for 3-STATE version Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Ordering Code: Order Number Package Number Package Description 74F273SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F273PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 DS009511
