74F273SCX ,Octal D flip-flopFeaturesYIdeal buffer for MOS microprocessor or memoryThe ’F273 has eight edge-triggered D-type fli ..
74F273SJ ,Octal D Flip-FlopFeaturesThe 74F273 has eight edge-triggered D-type flip-flops with
74F273PC-74F273SCX
Octal D flip-flop
TL/F/9511
54F/74F273
Octal
Flip-Flop
May 1995
54F/74F273
OctalD Flip-Flop
General Description
The ’F273has eight edge-triggered D-type flip-flops within-
dividualD inputs andQ outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear)all flip-flops simultaneously.
The registeris fully edge-triggered.The stateof eachDin-
put, one setup time beforethe LOW-to-HIGH clock tran-
sition,is transferredtothe corresponding flip-flop’sQout-
put.
All outputswillbe forced LOW independentlyof Clockor
Data inputsbya LOW voltage levelontheMR input.The
deviceis usefulforapplications wherethe trueoutput onlyis
requiredandthe Clockand Master Resetarecommontoall
storage elements.
Features Ideal bufferfor MOS microprocessoror memory Eight edge-triggeredD flip-flops Buffered common clock Buffered, asynchronous Master Reset See ’F377for clock enable version See ’F373for transparent latch version See ’F374for TRI-STATEÉ version Guaranteed 4000V minimum ESD protection
Commercial Military Package Package DescriptionNumber
74F273PC N20A 20-Lead (0.300× Wide) Molded Dual-In-Line
54F273DM (Note2) J20A 20-Lead CeramicDual-In-Line
74F273SC (Note1) M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC
74F273SJ (Note1) M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ
54F273FM(Note2) W20A 20-Lead Cerpack
54F273LM (Note2) E20A 20-Lead CeramicLeadless Chip Carrier,TypeC
Note 1:Devicesalso availablein13×reel. UsesuffixeSCXandSJX.
Note 2:Militarygrade devicewith environmentaland burn-in processing.Use suffixe DMQB, FMQBandLMQB.
Logic Symbols
TL/F/9511–3
IEEE/IEC
TL/F/9511–5
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M75/PrintedinU.S.A.
