74F192PC ,Up/Down Decade Counter with Separate Up/Down ClocksGeneral Descriptiondesigns. Individual preset inputs allow the circuit to be usedThe 74F192 is an u ..
74F193 ,Up/Down Binary Counter with Separate Up/Down Clocks54F/74F193Up/DownBinaryCounterwithSeparateUp/DownClocksNovember199454F/74F193Up/DownBinaryCounterwi ..
74F193PC ,Up/Down Binary Counter with Separate Up/Down ClocksGeneral Descriptionextra logic, thus simplifying multi-stage counter designs.The 74F193 is an up/do ..
74F193SC ,Up/Down Binary Counter with Separate Up/Down Clocks54F/74F193Up/DownBinaryCounterwithSeparateUp/DownClocksNovember199454F/74F193Up/DownBinaryCounterwi ..
74F193SCX ,Up/Down Binary Counter with Separate Up/Down Clocks74F193 Up/Down Binary Counter with Separate Up/Down ClocksApril 1988Revised September 200074F193Up/ ..
74F193SJ ,Up/Down Binary Counter with Separate Up/Down Clocks74F193 Up/Down Binary Counter with Separate Up/Down ClocksApril 1988Revised September 200074F193Up/ ..
74HCT390N ,Dual decade ripple counterINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT393 ,Dual 4-bit binary ripple counter
74HCT393 ,Dual 4-bit binary ripple counter
74HCT393 ,Dual 4-bit binary ripple counter
74HCT393D ,74HC/HCT393; Dual 4-bit binary ripple counterLogic diagram (one counter)5. Pinning information5.1 Pinning +& +&7 &3905&34 ..
74HCT393N ,Dual 4-bit binary ripple counterGENERAL DESCRIPTIONThe master resets are active-HIGH asynchronous inputsThe 74HC/HCT393 are high-sp ..
74F192PC
Up/Down Decade Counter with Separate Up/Down Clocks
74F192 Up/Down Decade Counter with Separate Up/Down Clocks April 1988 Revised March 1999 74F192 Up/Down Decade Counter with Separate Up/Down Clocks without extra logic, thus simplifying multistage counter General Description designs. Individual preset inputs allow the circuit to be used The 74F192 is an up/down BCD decade (8421) counter. as a programmable counter. Both the Parallel Load (PL) Separate Count Up and Count Down Clocks are used, and and the Master Reset (MR) inputs asynchronously override in either counting mode the circuits operate synchronously. the clocks. The outputs change state synchronously with the LOW-to- HIGH transitions on the clock inputs. Features Separate Terminal Count Up and Terminal Count Down � Guaranteed 4000V minimum ESD protection outputs are used as the clocks for a subsequent stage Ordering Code: Order Number Package Number Package Description 74F192SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F192PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 DS009496.prf
