74F174SCX ,Hex D-Type Flip-Flop with Master ResetFunctional Description Truth TableThe 74F174 consists of six edge-triggered D-type flip-flopsInputs ..
74F174SJ ,Hex D-Type Flip-Flop with Master ResetFeaturesYEdge-triggered D-type inputsThe ’F174 is a high-speed hex D flip-flop. The device isYused ..
74F174SJX ,Hex D-Type Flip-Flop with Master ResetFunctional Description Truth TableThe 74F174 consists of six edge-triggered D-type flip-flopsInputs ..
74F175 ,Quad D Flip-Flop54F/74F175QuadDFlip-FlopNovember199454F/74F175QuadDFlip-FlopGeneralDescription
74F175A ,Quad D flip-flop
74F175AD ,Quad D flip-flop
74HCT368D ,74HC/HCT368; Hex buffer/line driver; 3-state; invertingGENERAL DESCRIPTIONThe 74HC/HCT368 are high-speed Si-gate CMOS devicesand are pin compatible with l ..
74HCT368D ,74HC/HCT368; Hex buffer/line driver; 3-state; invertingINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT373D ,Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT373DB ,Octal D-type transparent latch; 3-stateapplications3-state true outputs. When LE is HIGH, data at the Dn• Common 3-state output enable inp ..
74HCT373N ,74HC/HCT373; Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT373PW ,Octal D-type transparent latch; 3-stateFEATURES input and an output enable (OE) input are common to alllatches.• 3-state non-inverting out ..
74F174PC-74F174SCX-74F174SJX
Hex D-Type Flip-Flop with Master Reset
74F174 Hex D-Type Flip-Flop with Master Reset April 1988 Revised September 2000 74F174 Hex D-Type Flip-Flop with Master Reset General Description Features The 74F174 is a high-speed hex D-type flip-flop. TheEdge-triggered D-type inputs device is used primarily as a 6-bit edge-triggered storageBuffered positive edge-triggered clock register. The information on the D inputs is transferred to Asynchronous common reset storage during the LOW-to-HIGH clock transition. The Guaranteed 4000V minimum ESD protection device has a Master Reset to simultaneously clear all flip-flops. Ordering Code: Order Number Package Number Package Description 74F174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 DS009489
