74F132SCX ,Quad 2-Input NAND Schmitt TriggerGeneral Descriptiontively speed-up slow input transitions, and provide differentThe F132 contains f ..
74F132SCX ,Quad 2-Input NAND Schmitt TriggerElectrical CharacteristicsMin Typ Max VSymbol Parameter Units ConditionsCCV Positive-going Threshol ..
74F132SJ ,Quad 2-Input NAND Schmitt Trigger74F132 Quad 2-Input NAND Schmitt TriggerApril 1988Revised September 200074F132Quad 2-Input NAND Sch ..
74F132SJX ,Quad 2-Input NAND Schmitt TriggerElectrical CharacteristicsMin Typ Max VSymbol Parameter Units ConditionsCCV Positive-going Threshol ..
74F132SJX ,Quad 2-Input NAND Schmitt TriggerGeneral Descriptiontively speed-up slow input transitions, and provide differentThe F132 contains f ..
74F133 ,13-input NAND gate
74HCT174DB ,Hex D-type flip-flop with reset; positive-edge triggerGENERAL DESCRIPTIONA LOW level on the MR input forces all outputs LOW,The 74HC/HCT174 are high-spee ..
74HCT174N ,Hex D-type flip-flop with reset; positive-edge triggerFEATURES The 74HC/HCT174 have six edge-triggered D-typeflip-flops with individual D inputs and Q ou ..
74HCT175D ,Quad D-type flip-flop with reset; positive-edge triggerLogic diagram74HC_HCT175 All information provided in this document is subject to legal disclaimers. ..
74HCT175N ,Quad D-type flip-flop with reset; positive-edge triggerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT175PW ,Quad D-type flip-flop with reset; positive-edge triggerFEATURES The 74HC/HCT175 have four edge-triggered, D-typeflip-flops with individual D inputs and bo ..
74HCT181N ,4-bit arithmetic logic unit
74F132PC-74F132SCX-74F132SJ-74F132SJX
Quad 2-Input NAND Schmitt Trigger
74F132 Quad 2-Input NAND Schmitt Trigger April 1988 Revised September 2000 74F132 Quad 2-Input NAND Schmitt Trigger ture. The Schmitt Trigger uses positive feedback to effec- General Description tively speed-up slow input transitions, and provide different The F132 contains four 2-input NAND gates which accept input threshold voltages for positive and negative-going standard TTL input signals and provide standard TTL out- transitions. This hysteresis between the positive-going and put levels. They are capable of transforming slowly chang- negative-going input threshold (typically 800 mV) is deter- ing input signals into sharply defined, jitter-free output mined by resistor ratios and is essentially insensitive to signals. In addition, they have a greater noise margin than temperature and supply voltage variations. conventional NAND gates. Each circuit contains a 2-input Schmitt Trigger followed by level shifting circuitry and a standard FAST output struc- Ordering Code: Order Number Package Number Package Description 74F132SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F132PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Function Table Unit Loading/Fan Out Inputs Outputs AB O U.L. Input I /I IH IL Pin Names Description LL H HIGH/LOW Output I /I OH OL LH H A , B Inputs 1.0/1.0 20 μA/−0.6 mA n n HL H O Outputs 50/33.3 −1 mA/20 mA n HH L H = HIGH Voltage Level L = LOW Voltage Level FAST is a registered trademark of © 2000 DS009477
