74F125SJ ,Quad Buffer (3-STATE)74F125 Quad Buffer (3-STATE)April 1988Revised September 200074F125Quad Buffer (3-STATE)
74F125SJ ,Quad Buffer (3-STATE)74F125 Quad Buffer (3-STATE)April 1988Revised September 200074F125Quad Buffer (3-STATE)
74F125SJX ,Quad Buffer (3-STATE)Features
74F125PC-74F125SC-74F125SCX-74F125SJ-74F125SJX
Quad Buffer (3-STATE)
74F125 Quad Buffer (3-STATE) April 1988 Revised September 2000 74F125 Quad Buffer (3-STATE) Features High impedance base inputs for reduced loading Ordering Code: Order Number Package Number Package Description 74F125SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F125PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Unit Loading/Fan Out Input I /I U.L. IH IL Pin Names Description Output I /I HIGH/LOW OH OL A , B Inputs 1.0/0.033 20 μA/−20 μA n n O Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) n Function Table Inputs Output A B O n n LL L LH H HX Z H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial © 2000 DS009475
