74F114PC ,Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and ClearsGeneral DescriptionQ HIGH.The 74F114 contains two high-speed JK flip-flops withAsynchronous Inputs: ..
74F11PC ,Triple 3-Input AND GateGeneral DescriptionThis device contains three independent gates, each ofwhich performs the logic AN ..
74F11PC. ,Triple 3-Input AND GateElectrical CharacteristicsSymbol Parameter 54F/74F Units V ConditionsCCMin Typ MaxV Input HIGH Volt ..
74F11SCX ,Triple 3-Input AND GateElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
74F11SJ ,Triple 3-Input AND GateGeneral DescriptionThis device contains three independent gates, each ofwhich performs the logic AN ..
74F11SJX ,Triple 3-Input AND GateGeneral DescriptionThis device contains three independent gates, each ofwhich performs the logic AN ..
74HCT153N ,Dual 4-input multiplexerFEATURES The 74HC/HCT153 have two The logic equations for the outputsidentical 4-input multiplexers ..
74HCT153N ,Dual 4-input multiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT153PW ,74HC/HCT153; Dual 4-input multiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT153PW ,74HC/HCT153; Dual 4-input multiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT154 ,4-to-16 line decoder/demultiplexer
74HCT154D ,4-to-16 line decoder/demultiplexerGeneral descriptionThe 74HC154; 74HCT154 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74F114PC
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
74F114 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears Simultaneous LOW signals on S and C force both Q and D D General Description Q HIGH. The 74F114 contains two high-speed JK flip-flops with Asynchronous Inputs: common Clock and Clear inputs. Synchronous state LOW input to S sets Q to HIGH level changes are initiated by the falling edge of the clock. Trig- D gering occurs at a voltage level of the clock and is not LOW input to C sets Q to LOW level D directly related to the transition time. The J and K inputs Clear and Set are independent of Clock can change when the clock is in either state without affect- Simultaneous LOW on C and S ing the flip-flop, provided that they are in the desired state D D during the recommended setup and hold times relative to makes both Q and Q HIGH the falling edge of the clock. A LOW signal on S or C D D prevents clocking and forces Q or Q HIGH, respectively. Ordering Code: Order Number Package Number Package Description 74F114SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F114PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 DS009474
