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74F114
Dual JK Negative Edge-Triggered Flip-Flop w/Common Clocks and Clears
TL/F/9474
74F114
Dual
Negative
Edge-Triggered
Flip-Flop
with
Common
Clocks
and
Clears
August 1995
74F114
Dual JK Negative Edge-Triggered Flip-Flop
with Common Clocks and Clears
General Description
The ’F114 containstwo high-speedJK flip-flops with com-
mon Clock and Clear inputs. Synchronous state changes
are initiatedbythe falling edgeofthe clock. Triggeringoc-
cursata voltage levelofthe clockandisnot directly relatedthe transition time. TheJandK inputscan change when
the clockisin either statewithout affectingthe flip-flop,pro-
vided that theyareinthe desired state duringthe recom-
mended setupand hold times relativetothe falling edgeof
the clock.A LOW signalonSDorCD prevents clockingand
forcesQorQ HIGH, respectively. Simultaneous LOWsig-
nalsonSDandCD force bothQandQ HIGH.
Asynchronous Inputs:
LOW inputtoSD setsQto HIGH level
LOW inputtoCD setsQto LOW level
ClearandSetare independentof Clock
Simultaneous LOWonCDandSD
makes bothQandQ HIGH
Features Guaranteed 4000V minimum ESD protection
Commercial Package PackageDescriptionNumber
74F114PC N14A 14-Lead (0.300× Wide) Molded Dual-In-Line
74F114SC (Note1) M14A 14-Lead (0.150× Wide) Molded Small Outline, JEDEC
Note1: Devicesalso availablein13×reel.UsesuffixeSCX.
Logic Symbols Connection Diagram
TL/F/9474–3
IEEE/IEC
TL/F/9474–5
PinAssignment
for SOIC andDIP
TL/F/9474–1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
