74F114 ,Dual JK Negative Edge-Triggered Flip-Flop w/Common Clocks and Clears
74F114 ,Dual JK Negative Edge-Triggered Flip-Flop w/Common Clocks and Clears74F114DualJKNegativeEdge-TriggeredFlip-FlopwithCommonClocksandClearsAugust199574F114DualJKNegativeE ..
74F114PC ,Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and ClearsGeneral DescriptionQ HIGH.The 74F114 contains two high-speed JK flip-flops withAsynchronous Inputs: ..
74F11PC ,Triple 3-Input AND GateGeneral DescriptionThis device contains three independent gates, each ofwhich performs the logic AN ..
74F11PC. ,Triple 3-Input AND GateElectrical CharacteristicsSymbol Parameter 54F/74F Units V ConditionsCCMin Typ MaxV Input HIGH Volt ..
74F11SCX ,Triple 3-Input AND GateElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
74HCT153N ,Dual 4-input multiplexerFEATURES The 74HC/HCT153 have two The logic equations for the outputsidentical 4-input multiplexers ..
74HCT153N ,Dual 4-input multiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT153PW ,74HC/HCT153; Dual 4-input multiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT153PW ,74HC/HCT153; Dual 4-input multiplexerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT154 ,4-to-16 line decoder/demultiplexer
74HCT154D ,4-to-16 line decoder/demultiplexerGeneral descriptionThe 74HC154; 74HCT154 is a high-speed Si-gate CMOS device and is pin compatiblew ..
74F113SCX
Dual JK Negative Edge-Triggered Flip-Flop
74F113 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop transferred to the outputs on the falling edge of the clock General Description pulse. The 74F113 offers individual J, K, Set and Clock inputs. Asynchronous input: When the clock goes HIGH the inputs are enabled and LOW input to S sets Q to HIGH level D data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip- Set is independent of clock flop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is Ordering Code: Order Number Package Number Package Description 74F113SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F113SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F113PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 DS009473
