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74F113
Dual Negative JK Edge-Triggered Flip-Flop
TL/F/9473
74F113
Dual
Negative
Edge-Triggered
Flip-Flop
August 1995
74F113
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’F113 offersindividualJ,K,Set andClock inputs. When
the clock goes HIGHthe inputsare enabledand data may entered. The logic leveloftheJandK inputs maybe
changed whenthe clock pulseis HIGHandthe flip-flopwill
perform accordingtothe Truth Tableas longas minimum
setupand hold timesare observed. Input datais transferredthe outputsonthe falling edgeofthe clock pulse.
Asynchronous input:
LOW inputtoSD setsQto HIGH level
Setis independentof clock
Features Guaranteed 4000V minimum ESD protection
Commercial Package PackageDescriptionNumber
74F113PC N14A 14-Lead (0.300× Wide) Molded Dual-In-Line
74F113SC (Note1) M14A 14-Lead (0.150× Wide) Molded Small Outline, JEDEC
74F113SJ(Note1) M14D 14-Lead (0.300× Wide) Molded Small Outline, EIAJ
Note1: Devicesalso availablein13×reel.Usesuffixe SCXandSJX.
Logic Symbols Connection Diagram
IEEE/IEC
TL/F/9473–6
PinAssignment
for SOIC andDIP
TL/F/9473–1
TL/F/9473–3 TL/F/9473–4
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
