74F112SCX ,Dual JK Negative Edge-Triggered Flip-FlopGeneral DescriptionQ HIGH.The 74F112 contains two independent, high-speed JK flip-Asynchronous Inpu ..
74F112SJ ,Dual JK Negative Edge-Triggered Flip-FlopGeneral DescriptionQ HIGH.The 74F112 contains two independent, high-speed JK flip-Asynchronous Inpu ..
74F112SJX ,Dual JK Negative Edge-Triggered Flip-FlopGeneral DescriptionQ HIGH.The 74F112 contains two independent, high-speed JK flip-Asynchronous Inpu ..
74F112SJX ,Dual JK Negative Edge-Triggered Flip-Flop74F112 Dual JK Negative Edge-Triggered Flip-FlopApril 1988Revised September 200074F112Dual JK Negat ..
74F113 ,Dual Negative JK Edge-Triggered Flip-Flop74F113DualJKNegativeEdge-TriggeredFlip-FlopAugust199574F113DualJKNegativeEdge-TriggeredFlip-FlopGen ..
74F113PC ,Dual JK Negative Edge-Triggered Flip-FlopGeneral Descriptionpulse.The 74F113 offers individual J, K, Set and Clock inputs.Asynchronous input ..
74HCT14N. ,74HC/HCT14; Hex inverting Schmitt triggerFEATURES DESCRIPTION•
74HCT14PW ,74HC/HCT14; Hex inverting Schmitt triggerPin configuration DHVQFN146.2 Pin description Table 2. Pin descriptionSymbol Pin Description1A to 6 ..
74HCT151 ,8-input multiplexer
74HCT151D ,8-input multiplexerGENERAL DESCRIPTIONThe 74HC/HCT151 are high-speed Si-gate CMOS devices and are pin compatible with ..
74HCT151N ,74HC/HCT151; 8-input multiplexerLogic diagram74HC_HCT151 All information provided in this document is subject to legal disclaimers. ..
74HCT153 ,Dual 4-input multiplexer
74F112PC-74F112SC-74F112SCX-74F112SJ-74F112SJX
Dual JK Negative Edge-Triggered Flip-Flop
74F112 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised September 2000 74F112 Dual JK Negative Edge-Triggered Flip-Flop Simultaneous LOW signals on S and C force both Q and D D General Description Q HIGH. The 74F112 contains two independent, high-speed JK flip- Asynchronous Inputs: flops with Direct Set and Clear inputs. Synchronous state LOW input to S sets Q to HIGH level changes are initiated by the falling edge of the clock. Trig- D gering occurs at a voltage level of the clock and is not LOW input to C sets Q to LOW level D directly related to the transition time. The J and K inputs Clear and Set are independent of clock can change when the clock is in either state without affect- Simultaneous LOW on C and S makes both Q ing the flip-flop, provided that they are in the desired state D D during the recommended setup and hold times relative to and Q HIGH the falling edge of the clock. A LOW signal on S or C D D prevents clocking and forces Q or Q HIGH, respectively. Ordering Code: Order Number Package Number Package Description 74F112SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F112PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 DS009472
