74F112 ,Dual JK Negative Edge-Triggered Flip-Flop74F112DualJKNegativeEdge-TriggeredFlip-FlopAugust199574F112DualJKNegativeEdge-TriggeredFlip-FlopGen ..
74F112PC ,Dual JK Negative Edge-Triggered Flip-FlopGeneral DescriptionQ HIGH.The 74F112 contains two independent, high-speed JK flip-Asynchronous Inpu ..
74F112SC ,Dual JK Negative Edge-Triggered Flip-FlopGeneral DescriptionQ HIGH.The 74F112 contains two independent, high-speed JK flip-Asynchronous Inpu ..
74F112SCX ,Dual JK Negative Edge-Triggered Flip-FlopGeneral DescriptionQ HIGH.The 74F112 contains two independent, high-speed JK flip-Asynchronous Inpu ..
74F112SJ ,Dual JK Negative Edge-Triggered Flip-FlopGeneral DescriptionQ HIGH.The 74F112 contains two independent, high-speed JK flip-Asynchronous Inpu ..
74F112SJX ,Dual JK Negative Edge-Triggered Flip-FlopGeneral DescriptionQ HIGH.The 74F112 contains two independent, high-speed JK flip-Asynchronous Inpu ..
74HCT14D. ,74HC/HCT14; Hex inverting Schmitt triggerFEATURES DESCRIPTION•
74HCT14DB ,Hex inverting Schmitt triggerLogic diagram (one Schmitt trigger)74HC_HCT14 All information provided in this document is subject ..
74HCT14D-T , Hex inverting Schmitt trigger
74HCT14D-T , Hex inverting Schmitt trigger
74HCT14D-T , Hex inverting Schmitt trigger
74HCT14N ,74HC/HCT14; Hex inverting Schmitt triggerINTEGRATED CIRCUITSDATA SHEET74HC14; 74HCT14Hex inverting Schmitt triggerProduct specification 2003 ..
74F112
Dual JK Negative Edge-Triggered Flip-Flop
TL/F/9472
74F112
Dual
Negative
Edge-Triggered
Flip-Flop
August 1995
74F112
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The ’F112 containstwo independent, high-speedJKflip-
flops with DirectSetand Clear inputs. Synchronous state
changesare initiatedbythe falling edgeofthe clock. Trig-
gering occursata voltage levelofthe clockandisnotdi-
rectly relatedtothe transition time.TheJandK inputscan
change whenthe clockisin either state without affecting
the flip-flop, providedthat theyareinthe desired statedur-
ingthe recommended setupand hold times relativetothe
falling edgeofthe clock.A LOW signalonSDorCD pre-
vents clockingand forcesQorQ HIGH, respectively. Simul-
taneous LOW signalsonSD andCD force bothQ andQ
HIGH.
Asynchronous Inputs:
LOW inputtoSD setsQto HIGH level
LOW inputtoCD setsQto LOW level
ClearandSetare independentof clock
Simultaneous LOWonCDandSD makes bothQ
andQ HIGH
Features Guaranteed 4000V minimum ESD protection
Commercial Package PackageDescriptionNumber
74F112PC N16E 16-Lead (0.300× Wide) Molded Dual-In-Line
74F112SC (Note1) M16A 16-Lead (0.150× Wide) Molded Small Outline, JEDEC
74F112SJ(Note1) M16D 16-Lead (0.300× Wide) Molded Small Outline, EIAJ
Note1: Devicesalso availablein13×reel.Usesuffixe SCXandSJX.
Logic Symbols Connection Diagram
TL/F/9472–3 TL/F/9472–4
IEEE/IEC
TL/F/9472–6
PinAssignment
forSOIC
TL/F/9472–1
TRI-STATEÉ isaregistered trademarkof National SemiconductorCorporation.
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
