74F10SCX ,Triple 3-Input NAND GateElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
74F10SCX ,Triple 3-Input NAND GateElectrical CharacteristicsVSymbol Parameter Min Typ Max Units ConditionsCCV Input HIGH Voltage 2.0 ..
74F10SCX ,Triple 3-Input NAND GateGeneral DescriptionThis device contains three independent gates, each ofwhich performs the logic NA ..
74F10SJ ,Triple 3-Input NAND GateGeneral DescriptionThis device contains three independent gates, each ofwhich performs the logic NA ..
74F10SJX ,Triple 3-Input NAND GateGeneral DescriptionThis device contains three independent gates, each ofwhich performs the logic NA ..
74F112 ,Dual JK Negative Edge-Triggered Flip-Flop74F112DualJKNegativeEdge-TriggeredFlip-FlopAugust199574F112DualJKNegativeEdge-TriggeredFlip-FlopGen ..
74HCT147D ,74HC/HCT147; 10-to-4 line priority encoderINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT147N ,74HC/HCT147; 10-to-4 line priority encoderINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT14D ,74HC/HCT14; Hex inverting Schmitt triggerPin configuration DIP14, SO14 and (T)SSOP14 Fig 5.
74HCT14D. ,74HC/HCT14; Hex inverting Schmitt triggerFEATURES DESCRIPTION•
74HCT14DB ,Hex inverting Schmitt triggerLogic diagram (one Schmitt trigger)74HC_HCT14 All information provided in this document is subject ..
74HCT14D-T , Hex inverting Schmitt trigger
74F10PC-74F10SC-74F10SCX-74F10SJ-74F10SJX
Triple 3-Input NAND Gate
74F10 Triple 3-Input NAND Gate April 1988 Revised September 2000 74F10 Triple 3-Input NAND Gate General Description This device contains three independent gates, each of which performs the logic NAND function. Ordering Code: Order Number Package Number Package Description 74F10SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F10SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F10PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Unit Loading/Fan Out Input I /I U.L. IH IL Pin Names Description HIGH/LOW Output I /I OH OL A , B , C Inputs 1.0/1.0 20 μA/−0.6 mA n n n O Outputs 50/33.3 −1 mA/20 mA n © 2000 DS009458
