74F1071MTCX ,18-Bit Undershoot/Overshoot Clamp and ESD Protection Device74F1071 18-Bit Undershoot/Overshoot ClampOctober 1994Revised October 200074F107118-Bit Undershoot/O ..
74F1071MTCX ,18-Bit Undershoot/Overshoot Clamp and ESD Protection Device74F1071 18-Bit Undershoot/Overshoot ClampOctober 1994Revised October 200074F107118-Bit Undershoot/O ..
74F1071SCX ,18-Bit Undershoot/Overshoot Clamp and ESD Protection DeviceElectrical CharacteristicsT = +25°CT = 0°C to +70°CA ASymbol Parameter Units ConditionsMin Typ Max ..
74F109 ,Positive J-Knot positive edge-triggered flip-flops54F/74F109DualJKPositiveEdge-TriggeredFlip-FlopNovember199454F/74F109DualJKPositiveEdge-TriggeredFl ..
74F109PC ,Dual JK# Positive Edge-Triggered Flip-FlopGeneral DescriptionLOW input to S sets Q to HIGH levelDThe F109 consists of two high-speed, complet ..
74F109SC ,Dual JK Positive Edge-Triggered Flip-FlopGeneral DescriptionLOW input to S sets Q to HIGH levelDThe F109 consists of two high-speed, complet ..
74HCT138 ,3-to-8 LINE DECODER/ DEMULTIPLEXER
74HCT138BQ ,3-to-8 line decoder, demultiplexer; invertingFEATURES The 74HC/HCT138 decoders accept three binaryweighted address inputs (A , A , A ) and when ..
74HCT138D ,74HC/HCT138; 3-to-8 line decoder/demultiplexer; invertingLogic diagram5. Pinning information5.1 Pinning 74HC138BQ74HCT138BQ74HC13874HCT138terminal 1index ar ..
74HCT138N ,3-to-8 line decoder, demultiplexer; invertingINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT138PW ,74HC/HCT138; 3-to-8 line decoder/demultiplexer; invertingLogic diagram5. Pinning information5.1 Pinning 74HC138BQ74HCT138BQ74HC13874HCT138terminal 1index ar ..
74HCT138PW ,74HC/HCT138; 3-to-8 line decoder/demultiplexer; invertingGeneral descriptionThe 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible ..
74F1071MSA-74F1071MSAX-74F1071MTCX-74F1071SCX
18-Bit Undershoot/Overshoot Clamp and ESD Protection Device
74F1071 18-Bit Undershoot/Overshoot Clamp October 1994 Revised October 2000 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device General Description Features The 74F1071 is an 18-bit undershoot/overshoot clamp18-bit array structure in 20-pin package which is designed to limit bus voltages and also to protectFAST Bipolar voltage clamping action more sensitive devices from electrical overstress due to Dual center pin grounds for min inductance electrostatic discharge (ESD). The inputs of the device Robust design for ESD protection aggressively clamp voltage excursions nominally at 0.5V Low input capacitance below and 7V above ground. Optimum voltage clamping for 5V CMOS/TTL applications Ordering Code: Order Number Package Number Package Description 74F1071SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74F1071MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F1071MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Note: Simplified Component Representation FAST is a registered trademark of . © 2000 DS011685
