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Partno	Mfg	Dc	Qty	Available	Descript
74F04SC	NS	N/a	50	avai	Hex Inverter

74F04SC ,Hex InverterElectrical CharacteristicsSymbol Parameter 54F/74F Units V ConditionsCCMin Typ MaxV Input HIGH Volt ..
74F04SCX ,Hex InverterGeneral DescriptionThis device contains six independent gates, each of whichperforms the logic INVE ..
74F04SJ ,Hex InverterGeneral DescriptionThis device contains six independent gates, each of whichperforms the logic INVE ..
74F04SJX ,Hex InverterGeneral DescriptionThis device contains six independent gates, each of whichperforms the logic INVE ..
74F08 ,Quad 2-Input AND GateGeneral DescriptionThis device contains four independent gates, each of whichperforms the logic AND ..
74F08PC ,Quad 2-Input AND GateGeneral DescriptionThis device contains four independent gates, each of whichperforms the logic AND ..
74HCT10D ,74HC/HCT10; Triple 3-input NAND gateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT10DB ,74HC/HCT10; Triple 3-input NAND gateFEATURES• Output capability: standard• I category: SSICC
74HCT10N ,74HC/HCT10; Triple 3-input NAND gatePin configuration. Fig.2 Logic symbol.FUNCTION TABLEINPUTS OUTPUTnA nB nC nYLLL HLL H HLHL HLH H H ..
74HCT10N ,74HC/HCT10; Triple 3-input NAND gateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HCT112D ,dual JK flip-flop with set and reset; negative-edge triggerGENERAL DESCRIPTIONset-up time prior to the HIGH-to-LOW clock transition forThe 74HC/HCT112 are hig ..
74HCT112D ,dual JK flip-flop with set and reset; negative-edge triggerFEATURES The set and reset inputs, when LOW, set or reset theoutputs as shown in the function table ..

74F04SC
Hex Inverter
54F/74F04
Hex Inverter
General Description
This device containssix independent gates, eachof which
performsthe logic INVERT function.
Features Guaranteed 4000V minimum ESD protection
Ordering Code: See Section0
Commercial Military Package Package Description
Number
74F04PC N14A 14-Lead (0.300" Wide) Molded Dual-In-Line
54F04DM (Note2) J14A 14-Lead Ceramic Dual-In-Line
74F04SC (Note1) M14A 14-Lead (0.150" Wide) Molded Small Outline, JEDEC
74F04SJ (Note1) M14D 14-Lead (0.300" Wide) Molded Small Outline, EIAJ
54F04FM (Note2) W14B 14-Lead Cerpack
54F04LM (Note2) E20A 20-Lead Ceramic Leadless Chip Carrier, TypeC
Note1: Devicesalso availablein13"reel.Use suffix= SCXandSJX.
Note2: Military gradedevicewith environmentaland burn-in processing. Usesuffix= DMQB, FMQBand LMQB.
Logic Symbol
Connection Diagrams
TRI-STATE®isa registeredtrademark ofNationalSemiconductor Corporation.
IEEE/IEC
DS009456-3
Pin Assignmentfor
DIP, SOICand Flatpak
DS009456-2
Pin Assignment
for LCC
DS009456-1
November 1994
54F/74F04
Hex
Inverter
54F/74F04 1997NationalSemiconductor Corporation DS009456 1
DSXXX

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