SN74CBTLV16211GR ,Low-Voltage 24-Bit FET Bus Switch/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74CBTLV16211GR ,Low-Voltage 24-Bit FET Bus Switchlogic diagram (positive logic)2 541A1 1B1SW14 421A12 1B12SW561OE15 412A1 SW 2B128 292A12 SW 2B12552 ..
SN74CBTLV16211VR ,Low-Voltage 24-Bit FET Bus Switchmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74CBTLV16212DGGR , LOW-VOLTAGE 24-BIT FET BUS-EXCHANGE SWITCH
SN74CBTLV16212DL ,Low-Voltage 24-Bit FET Bus-Exchange Switch/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74CBTLV16212GR ,Low-Voltage 24-Bit FET Bus-Exchange Switchlogic diagram (positive logic)2 541A1 1B1SWSWSW3 53SW 1B21A227 3012A1 12B1SWSWSW28 2912A2 SW 12B21S ..
SN74S482N ,4-Bit-Slice Expandable Control Elements 20-PDIP 0 to 70
SN74S51DR , AND-OR-INVERT GATES
SN74S65DR ,4-2-3-2 Input AND-OR-invert Gates 14-SOIC 0 to 70
SN74S74 ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Preset And Clearq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
SN74S74D ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Preset And Clearq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
SN74S74N ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Preset And Clearq Package Options Include Plastic "Small SN5474 . . .J PACKAGEOutline" Packages. Ceramic Chip Carri ..
74CBTLV16211GRG4-SN74CBTLV16211-SN74CBTLV16211DL-SN74CBTLV16211GR-SN74CBTLV16211VR
Low-Voltage 24-Bit FET Bus Switch 56-SSOP -40 to 85
Ioff Supports Partial-Power-Down ModeOperation Latch-Up Performance Exceeds 250 mA Per
JESD 17 ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering informationThe SN74CBTLV16211 provides 24 bits of
high-speed bus switching. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
The device is organized as dual 12-bit bus
switches with separate output-enable (OE)
inputs. It can be used as two 12-bit bus switches
or as one 24-bit bus switch. When OE is low, the
associated 12-bit bus switch is on, and port A is
connected to port B. When OE is high, the switch
is open, and the high-impedance state exists
between the two ports.
This device is fully specified for
partial-power-down applications using Ioff . The Iofffeature ensures that damaging current will not
backflow through the device when it is powered
down. The device has isolation during power off.
To ensure the high-impedance state during power
up or power down, OE should be tied to VCCthrough a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
ORDERING INFORMATION Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
1A11
1A12
2A1
2A2
VCC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
2A11
2A12
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B11
2B12
NC − No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
