SN74CBT16245DGGR ,16-Bit FET Bus Switchmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74CBT16245DGGR ,16-Bit FET Bus Switchlogic diagram (positive logic)47 21A1 1B137 121A8 1B8481OE36 132A1 2B126 232A8 2B8252OE†absolute
SN74CBT16245DL ,16-Bit FET Bus Switchmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74CBT16292 ,12-Bit 1-OF-2 FET Multiplexer/Demultiplexer With Internal Pulldown Resistorsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74CBT16292DGGR ,12-Bit 1-OF-2 FET Multiplexer/Demultiplexer With Internal Pulldown ResistorsSN74CBT16292 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXERWITH INTERNAL PULLDOWN RESISTORSSCDS053E – ..
SN74CBT16292DGVR ,12-Bit 1-OF-2 FET Multiplexer/Demultiplexer With Internal Pulldown Resistorsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74S00 ,Quad 2-input positive-NAND gates SDLS025D–DECEMBER 1983–REVISED MAY 20175 Pin Configuration and FunctionsSN5400 J, SN54xx00 J and W ..
SN74S00N ,Quad 2-input positive-NAND gatesPin Functions (continued)PINI/O DESCRIPTIONCDIP, CFP, SOIC, SO CFPNAME LCCCPDIP, SO, SSOP (SN74xx00 ..
SN74S00NSR , QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SN74S00NSR , QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SN74S02D ,Quad 2-input positive-NOR gates
SN74S03 ,QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS
74CBT16245DGGRE4-74CBT16245DGVRG4-SN74CBT16245DGGR-SN74CBT16245DL
16-Bit FET Bus Switch 48-TSSOP -40 to 85
TTL-Compatible Input Levels Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
descriptionThe SN74CBT16245 device provides 16 bits of
high-speed TTL-compatible bus switching in a
standard ’16245 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
The device is organized as two 8-bit low-impedance
switches with separate output-enable (OE) inputs.
When OE is low, the switch is on, and data can
flow from the A port to the B port, or vice versa.
When OE is high, the switch is open, and the
high-impedance state exists between the two
ports.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit bus switch)Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
NC – No internal connection
