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74AVCH1T45DCKRG4-SN74AVCH1T45DBVR -SN74AVCH1T45DCKR-SN74AVCH1T45DCKT-SN74AVCH1T45YZPR
Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs 6-SOT-23 -40 to 85
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SN74AVCH1T45SCES598E –JULY 2004–REVISED MARCH 2016
SN74AVCH1T45 Single-Bit Dual-Supply Bus Transceiver
With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs Features Availablein the Texas Instruments NanoStar™
and NanoFree™ Packages Control Inputs (DIR) VIH and VIL Levels Are
Referencedto VCCA Voltage Bus Holdon Data Inputs Eliminates the Needfor
External Pullup and Pulldown Resistors VCC Isolation Fully Configurable Dual-Rail Design I/Os Are 4.6-V Tolerant Ioff Supports Partial-Power-Down Mode Operation Typical Max Data Rates 500 Mbps (1.8-Vto 3.3-V Translation) 320 Mbps (<1.8-Vto 3.3-V Translation) 320 Mbps (Translateto 2.5Vor 1.8V) 280 Mbps (Translateto 1.5V) 240 Mbps (Translateto 1.2V) Latch-Up Performance Exceeds 100 mA Per
JESD 78, ClassII ESD Protection Exceeds JESD22 Human-Body Model (A114-A): 2000V Machine Model (A115-A): 200V Charged-Device Model (C101): 1000V
Applications Personal Electronics Industrial Enterprise Telecommunications
DescriptionThe SN74AVCH1T45isa single-bit noninverting bus
transceiver that uses two separate configurable
power-supply rails. TheA portis designedto track
VCCA, which accepts any supply voltage from 1.2Vto
3.6 V. TheB portis designedto track VCCB, which
also accepts any supply voltage from 1.2Vto 3.6V.
This allows for universal low-voltage bidirectional
translation between anyof the 1.2-V, 1.5-V, 1.8-V,
2.5-V, and 3.3-V voltage nodes.
The SN74AVCH1T45is designed for asynchronous
communication between two data buses. The device
transmits data from either theA busto theB bus,or
from theB busto theA bus, depending upon the
logic levelat the direction-control (DIR) input.
The SN74AVCH1T45is designed so that the DIR
inputis referencedto VCCA.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
