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74AUP1G57GMPb-freeN/a2444avaiLow-power configurable multiple function gate
74AUP1G57GMNXPN/a15000avaiLow-power configurable multiple function gate


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74AUP1G57GM
Low-power configurable multiple function gate
1. General description
The 74AUP1G57 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
The 74AUP1G57 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
2. Features and benefits Wide supply voltage range from 0.8 Vto 3.6V High noise immunity ESD protection: HBM JESD22-A114F exceeds 5000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101E exceeds 1000V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation Multiple package options Specified from 40 Cto+85 C and 40 Cto+125C
74AUP1G57
Low-power configurable multiple function gate
Rev. 6 — 15 August 2012 Product data sheet
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
74AUP1G57GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74AUP1G57GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 1.45 0.5 mm
SOT886
74AUP1G57GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 11 0.5 mm
SOT891
74AUP1G57GN 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 0.9 1.0 0.35 mm
SOT1115
74AUP1G57GS 40 C to +125C XSON6 extremely thin small outline package; no leads; terminals; body 1.0 1.0 0.35 mm
SOT1202
Table 2. Marking
74AUP1G57GW aC
74AUP1G57GM aC
74AUP1G57GF aC
74AUP1G57GN aC
74AUP1G57GS aC
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H= HIGH voltage level; L= LOW voltage level.
Table 3. Pin description 1 data input
GND 2 ground (0V) 3 data input 4 data output
VCC 5 supply voltage 6 data input
Table 4. Function table[1] LH H L LH H L L L HL L H HH
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5. Function selection table
2-input AND see Figure5
2-input AND with both inputs inverted see Figure8
2-input NAND with inverted input see Figure 6 and Figure7
2-input OR with inverted input see Figure 6 and Figure7
2-input NOR see Figure8
2-input NOR with both inputs inverted see Figure5
2-input XNOR see Figure9
Inverter see Figure10
Buffer see Figure11
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
VCC supply voltage 0.5 +4.6 V
IIK input clamping current VI <0V 50 - mA input voltage [1] 0.5 +4.6 V
IOK output clamping current VO <0V 50 - mA output voltage Active mode and Power-down mode [1] 0.5 +4.6 V output current VO =0 VtoVCC - 20 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb= 40 C to +125C [2] -250 mW
Table 7. Recommended operating conditions
VCC supply voltage 0.8 3.6 V input voltage 0 3.6 V output voltage Active mode 0 VCC V
Power-down mode; VCC =0V 0 3.6 V
Tamb ambient temperature 40 +125 C
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
10. Static characteristicsTable 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = 25 C
VOH HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8Vto 3.6V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.75  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.11 - - V
IO = 1.9 mA; VCC = 1.65 V 1.32 - - V
IO = 2.3 mA; VCC = 2.3 V 2.05 - - V
IO = 3.1 mA; VCC = 2.3 V 1.9 - - V
IO = 2.7 mA; VCC = 3.0 V 2.72 - - V
IO = 4.0 mA; VCC = 3.0 V 2.6 - - V
VOL LOW-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8Vto 3.6V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.31 V
IO = 1.9 mA; VCC = 1.65 V - - 0.31 V
IO = 2.3 mA; VCC = 2.3 V - - 0.31 V
IO = 3.1 mA; VCC = 2.3 V - - 0.44 V
IO = 2.7 mA; VCC = 3.0 V - - 0.31 V
IO = 4.0 mA; VCC = 3.0 V - - 0.44 V input leakage current VI = GND to 3.6 V; VCC =0Vto3.6V - - 0.1 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC =0V - - 0.2 A
IOFF additional power-off leakage
current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.2 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 0.5 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V 40 A input capacitance VI = GND or VCC; VCC =0Vto3.6V - 1.1 - pF output capacitance VO = GND; VCC =0V - 1.7 - pF
Tamb = 40 C to +85C
VOH HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8Vto 3.6V VCC  0.1 - - V
IO = 1.1 mA; VCC = 1.1 V 0.7  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 1.03 - - V
IO = 1.9 mA; VCC = 1.65 V 1.30 - - V
IO = 2.3 mA; VCC = 2.3 V 1.97 - - V
IO = 3.1 mA; VCC = 2.3 V 1.85 - - V
IO = 2.7 mA; VCC = 3.0 V 2.67 - - V
IO = 4.0 mA; VCC = 3.0 V 2.55 - - V
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
VOL LOW-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8Vto 3.6V - - 0.1 V
IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V
IO = 1.7 mA; VCC = 1.4 V - - 0.37 V
IO = 1.9 mA; VCC = 1.65 V - - 0.35 V
IO = 2.3 mA; VCC = 2.3 V - - 0.33 V
IO = 3.1 mA; VCC = 2.3 V - - 0.45 V
IO = 2.7 mA; VCC = 3.0 V - - 0.33 V
IO = 4.0 mA; VCC = 3.0 V - - 0.45 V input leakage current VI = GND to 3.6 V; VCC =0Vto3.6V - - 0.5 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A
IOFF additional power-off leakage
current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.6 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 0.9 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V 50 A
Tamb = 40 C to +125C
VOH HIGH-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8Vto 3.6V VCC  0.11- - V
IO = 1.1 mA; VCC = 1.1 V 0.6  VCC -- V
IO = 1.7 mA; VCC = 1.4 V 0.93 - - V
IO = 1.9 mA; VCC = 1.65 V 1.17 - - V
IO = 2.3 mA; VCC = 2.3 V 1.77 - - V
IO = 3.1 mA; VCC = 2.3 V 1.67 - - V
IO = 2.7 mA; VCC = 3.0 V 2.40 - - V
IO = 4.0 mA; VCC = 3.0 V 2.30 - - V
VOL LOW-level output voltage VI = VT+ or VT
IO = 20 A; VCC = 0.8Vto 3.6V - - 0.11 V
IO = 1.1 mA; VCC = 1.1 V - - 0.33  VCCV
IO = 1.7 mA; VCC = 1.4 V - - 0.41 V
IO = 1.9 mA; VCC = 1.65 V - - 0.39 V
IO = 2.3 mA; VCC = 2.3 V - - 0.36 V
IO = 3.1 mA; VCC = 2.3 V - - 0.50 V
IO = 2.7 mA; VCC = 3.0 V - - 0.36 V
IO = 4.0 mA; VCC = 3.0 V - - 0.50 V input leakage current VI = GND to 3.6 V; VCC =0Vto3.6V - - 0.75 A
IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC =0V - - 0.75 A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
11. Dynamic characteristics
IOFF additional power-off leakage
current
VI or VO = 0 V to 3.6 V;
VCC =0Vto0.2V 0.75 A
ICC supply current VI = GND or VCC; IO = 0A;
VCC= 0.8Vto 3.6V 1.4 A
ICC additional supply current VI = VCC  0.6 V; IO = 0A;
VCC =3.3V 75 A
Table 8. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground=0 V); for test circuit, see Figure 13.
CL = 5 pF
tpd propagation delay A,B andCtoY;
see Figure12
[2]
VCC = 0.8 V - 22.6 - - - - ns
VCC = 1.1 V to 1.3 V 2.8 6.5 12.6 2.5 13.0 13.2 ns
VCC = 1.4 V to 1.6 V 2.2 4.6 7.6 2.5 8.2 8.6 ns
VCC = 1.65 V to 1.95 V 2.1 3.9 6.2 2.0 6.8 7.2 ns
VCC = 2.3 V to 2.7 V 2.0 3.1 4.5 1.8 5.1 5.3 ns
VCC = 3.0 V to 3.6 V 1.8 2.8 3.9 1.5 4.1 4.3 ns
CL = 10 pF
tpd propagation delay A,B andCtoY;
see Figure12
[2]
VCC = 0.8 V - 26.1 - - - - ns
VCC = 1.1 V to 1.3 V 3.2 7.3 14.4 2.8 14.9 15.2 ns
VCC = 1.4 V to 1.6 V 2.6 5.2 8.7 2.8 9.3 9.8 ns
VCC = 1.65 V to 1.95 V 2.5 4.5 7.0 2.2 7.8 8.2 ns
VCC = 2.3 V to 2.7 V 2.4 3.7 5.2 2.1 5.9 6.2 ns
VCC = 3.0 V to 3.6 V 2.3 3.4 4.6 1.9 4.9 5.1 ns
CL = 15 pF
tpd propagation delay A,B andCtoY;
see Figure12
[2]
VCC = 0.8 V - 31.6 - - - - ns
VCC = 1.1 V to 1.3 V 3.4 8.0 15.7 3.1 16.7 17.0 ns
VCC = 1.4 V to 1.6 V 2.8 5.7 9.4 3.1 10.4 10.9 ns
VCC = 1.65 V to 1.95 V 2.6 4.9 7.7 2.5 8.7 9.2 ns
VCC = 2.3 V to 2.7 V 2.6 4.1 5.7 2.4 6.5 6.9 ns
VCC = 3.0 V to 3.6 V 2.5 3.8 5.0 2.2 5.5 5.7 ns
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
[1] All typical values are measured at nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] All specified values are the average typical values over all stated loads.
[4] CPD is used to determine the dynamic power dissipation (PD in W). =CPD VCC2fi N+ (CL VCC2 fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in V;= number of inputs switching;
(CL VCC2fo)= sum of the outputs.
CL = 30 pF
tpd propagation delay A,B andCtoY;
see Figure12
[2]
VCC = 0.8 V - 37.8 - - - - ns
VCC = 1.1 V to 1.3 V 4.6 10.4 20.9 3.9 21.8 22.3 ns
VCC = 1.4 V to 1.6 V 3.6 7.4 12.2 3.8 13.4 14.1 ns
VCC = 1.65 V to 1.95 V 3.5 6.2 9.9 3.1 11.1 11.8 ns
VCC = 2.3 V to 2.7 V 3.4 5.2 7.4 3.1 8.3 8.8 ns
VCC = 3.0 V to 3.6 V 3.2 4.9 6.6 2.8 7.0 7.4 ns
CL = 5 pF, 10 pF, 15 pF and 30 pF
CPD power dissipation
capacitance
fi = 1 MHz; VI =GNDto VCC [3][4]
VCC = 0.8 V - 2.6 - - - - pF
VCC = 1.1 V to 1.3 V - 2.8 - - - - pF
VCC = 1.4 V to 1.6 V - 2.9 - - - - pF
VCC = 1.65 V to 1.95 V - 3.1 - - - - pF
VCC = 2.3 V to 2.7 V - 3.7 - - - - pF
VCC = 3.0 V to 3.6 V - 4.3 - - - - pF
Table 9. Dynamic characteristics …continued
Voltages are referenced to GND (ground=0 V); for test circuit, see Figure 13.
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
12. Waveforms
Table 10. Measurement points
0.8 V to 3.6 V 0.5  VCC 0.5  VCC VCC  3.0 ns
NXP Semiconductors 74AUP1G57
Low-power configurable multiple function gate
[1] For measuring enable and disable times, RL = 5 k For measuring propagation delays, set-up and hold times, and pulse width, =1M.
Table 11. Test data
0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2  VCC
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