74ALVTH16245VRG4 ,2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs 48-TVSOP -40 to 85 SCES066G − JUNE 1 ..
74ALVTH16374GR E4 , 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
74ALVTH16374GRE4 , 2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
74AS174 , HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
74AS175B , HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
74AUC1GU04DCKRG4 ,Single Inverter Gate 5-SC70 -40 to 85Electrical Characteristics....... 59.6 Glossary..... 96.6 Switching Characteristics: C = 15 pF.... ..
74HC573PW ,74HC/HCT573; Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC574D ,74HC/HCT574; Octal D-type flip-flop; positive edge-trigger; 3-stateLogic diagram74HC_HCT574 All information provided in this document is subject to legal disclaimers. ..
74HC574DB ,74HC/HCT574; Octal D-type flip-flop; positive edge-trigger; 3-stateapplications. A clock (CP)CCthe “564”, but has non-invertingand an output enable (OE) input areoutp ..
74HC574N ,Octal D-type flip-flop; positive edge-trigger; 3-statePin configuration DIP20 and SO20 Fig 6.
74HC574PW ,74HC/HCT574; Octal D-type flip-flop; positive edge-trigger; 3-stateFeatures and benefits 3-state non-inverting outputs for bus oriented
74HC58D ,Dual AND-OR gateGENERAL DESCRIPTIONThe 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low po ..
74ALVTH16245VRG4-SN74ALVTH16245DL-SN74ALVTH16245VR
2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs 48-TSSOP -40 to 85
Input and Output Voltages With 2.3-V to
3.6-V VCC) Typical V OLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C High Drive (−32/64 mA at 3.3-V VCC)Ioff and Power-Up 3-State Support Hot
Insertion Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating Flow-Through Architecture Facilitates
Printed Circuit Board Layout Distributed VCC and GND Pins Minimize
High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
descriptionThe ’ALVTH16245 devices are 16-bit (dual-octal)
noninverting 3-state transceivers designed for
2.5-V or 3.3-V VCC operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively
isolated.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
