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74ALVCH16841-74ALVCH16841DGG
20-bit bus interface D-type latch 3-State
Product specification
IC24 Data Handbook
1998 Jul 27
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
FEATURES Wide supply voltage range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A Wide supply voltage range of 1.2V to 3.6V CMOS low power consumption Direct interface with TTL levels MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise
and ground bounce Current drive ±24 mA at 3.0 V All inputs have bus hold circuitry Output drive capability 50Ω transmission lines @ 85°C 3-State non-inverting outputs for bus oriented applications
DESCRIPTIONThe 74ALVCH16841 has two 10-bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE) and output enable (nOE)
control gates.
When nOE is LOW, the data in the registers appears at the outputs.
When nOE is High the outputs are in High-impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16841 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in μW):
PD = CPD × VCC 2 × fi + (CL × VCC 2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC 2 × fo) = sum of outputs.
ORDERING INFORMATION
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
PIN DESCRIPTION
FUNCTION TABLE= High voltage level= Low voltage level= Don’t care= High impedance “off” state
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
BUS HOLD CIRCUIT
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGSIn accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTE: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
NOTES: All typical values are at Tamb = 25°C. Valid for data inputs of bus hold parts.
Philips Semiconductors Product specification
74ALVCH1684120-bit bus interface D-type latch (3-State)
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGEGND = 0V; tr = tf ≤ 2.0ns; CL = 30pF
NOTE: All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7VGND = 0V; tr = tf ≤ 2.5ns; CL = 50pF
NOTES: All typical values are measured Tamb = 25°C. Typical value is measured at VCC = 3.3V
