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74ALVCH16823DL ,18-bit bus-interface D-type flip-flop with reset and enable (3-State)
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74ALVCH16823DGG-74ALVCH16823DL
18-bit bus-interface D-type flip-flop with reset and enable (3-State)
Product specification
IC24 Data Handbook
1998 Jul 29
Philips Semiconductors Product specification
74ALVCH1682318-bit D-type flip-flop (3-State)
FEATURES Wide supply voltage range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive ± 24 mA at 3.0 V Multibyteflow-through standard pin-out architecture Low inductance multiple VCC and GND pins to minimize noise and
ground bounce All data inputs have bus hold Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTIONThe 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-state outputs for bus
oriented applications. Incorporates bushold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs. The74ALVCH16823 consists of two sections of nine
edge-triggered flip-flops. A clock (CP) input, an output-enable (OE)
input, a Master reset (MR) input and a clock-enable( CE) input are
provided for each total 9-bit section.
With the clock-enable (CE) input LOW, the D-type flip-flops will store
the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH CP transition. Taking CE
HIGH disables the clock buffer, thus latching the outputs. Taking the
Master reset (MR) input LOW causes all the Q outputs to go LOW
independently of the clock.
When OE is LOW, the contents of the flip-flops are available at the
outputs. When the OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of flip-flops.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
NOTES: CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC 2 × fi + (CL × VCC 2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
Philips Semiconductors Product specification
74ALVCH1682318-bit D-type flip-flop (3-State)
PIN DESCRIPTION
PIN CONFIGURATION
LOGIC SYMBOL
Philips Semiconductors Product specification
74ALVCH1682318-bit D-type flip-flop (3-State)
LOGIC SYMBOL (IEEE/IEC)
BUS HOLD CIRCUIT
LOGIC DIAGRAM
Philips Semiconductors Product specification
74ALVCH1682318-bit D-type flip-flop (3-State)
FUNCTION TABLE= HIGH voltage level= HIGH voltage level one set-up time prior to the Low-to-High clock transition= LOW voltage level = LOW voltage level one set-up time prior to the Low-to-High clock transition= Don’t care= HIGH impedance “off” state= LOW to High clock transition
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGSIn accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).
Philips Semiconductors Product specification
74ALVCH1682318-bit D-type flip-flop (3-State)
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
NOTES:
