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74ALVCH16821DGG-74ALVCH16821DL
20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State
Product specification
IC24 Data Handbook
1998 May 29
Philips Semiconductors Product specification
74ALVCH1682120-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
FEATURES Wide supply voltage range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A Current drive ± 24 mA at 3.0 V CMOS low power consumption Direct interface with TTL levels MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple VCC and ground pins for minimum noise
and ground bounce All data inputs have bus hold Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTIONThe 74ALVCH16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16821 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATAGND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
NOTE: CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
Philips Semiconductors Product specification
74ALVCH1682120-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
PIN DESCRIPTION
PIN CONFIGURATION
FUNCTION TABLE= HIGH voltage level= LOW voltage level= Don’t care= High impedance OFF state= LOW to HIGH clock transition= Not a LOW-to-HIGH clock transition
LOGIC SYMBOL
Philips Semiconductors Product specification
74ALVCH1682120-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
Philips Semiconductors Product specification
74ALVCH1682120-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGSIn accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
NOTE: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74ALVCH1682120-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
NOTES: All typical values are at Tamb = 25°C. Valid for data inputs of bus hold parts.
