Home ›  7 › 79 > 74ALVCH16374,Low Voltage 16-Bit D-Type Flip-Flop with Bushold

74ALVCH16374 Fast Delivery,Good Price
Part Number:

If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email

Partno	Mfg	Dc	Qty	Available	Descript
74ALVCH16374	TI	N/a	69	avai	Low Voltage 16-Bit D-Type Flip-Flop with Bushold
74ALVCH16374	PH	N/a	78	avai	Low Voltage 16-Bit D-Type Flip-Flop with Bushold
74ALVCH16374	PHILIPS	N/a	27	avai	Low Voltage 16-Bit D-Type Flip-Flop with Bushold
74ALVCH16374	HIT	N/a	106	avai	Low Voltage 16-Bit D-Type Flip-Flop with Bushold

74ALVCH16374 ,Low Voltage 16-Bit D-Type Flip-Flop with BusholdAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
74ALVCH16374 ,Low Voltage 16-Bit D-Type Flip-Flop with Busholdapplications with output compatibility up to 3.6V.CC

---

74ALVCH16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP FLOP (3-STATE)WITH 3.6V TOLERANT INPUTS AND OUTPUTS
1/11February 2003 3.6V TOLERANT INPUTS AND OUTPUTS HIGH SPEED:
tPD= 4.2ns (MAX.)at VCC =3.0to 3.6VPD= 5.3ns (MAX.)atVCC =2.3to 2.7V
tPD= 6.5ns (MAX.)at VCC =1.65V POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE:OH|=IOL= 24mA (MIN)atVCC =3.0VOH|=IOL= 18mA (MIN)atVCC =2.3VOH|=IOL =4mA (MIN)atVCC= 1.65V OPERATING VOLTAGE RANGE:CC (OPR)= 1.65Vto 3.6V PIN AND FUNCTION COMPATIBLE WITH SERIES 16374 BUS HOLD PROVIDED ON DATA INPUTS LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17) ESD PERFORMANCE:
HBM> 2000V (MIL STD 883 method 3015);> 200V
DESCRIPTION
The 74ALVCH16374isa low voltage CMOS 16
BIT D-TYPE FLIP-FLOP with3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and five-layer metal wiringC2 MOS
technology.Itis ideal for low power and very high
speed 1.65 to 3.6V applications;it can be
interfacedto 3.6V signal environment for both
inputs and outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enable
inputs (nOE). thepositivetransitionof the (nCK), thenQ
outputs will be setto the logic state that were
setupat the nD inputs.
While the (nOE) inputis low, the outputs (nQ) willina normal state (HIGHor LOW logic level)
and while high level the outputs will beina high
impedance state. Any output control does not
affect the internal operationof flip flops; thatis, the
old data can be retainedor the new data can be
entered even while the outputs are off.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ALVCH16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
ORDER CODES
PIN CONNECTION
74ALVCH16374
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE: Don‘t Care: High Impedance
IEC LOGIC SYMBOLS
74ALVCH16374
3/11
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
AbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not impliedIO absolute maximum rating mustbe observedVO VCC
RECOMMENDED OPERATING CONDITIONSVIN from 0.8Vto2Vat VCC =3.0V
74ALVCH16374
4/11 SPECIFICATIONS
74ALVCH16374
5/11 ELECTRICAL CHARACTERISTICS
74ALVCH16374
6/11
CAPACITIVE CHARACTERISTICS CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load. (Referto Test Circuit). Average operating currentcanbe obtainedbythe following equation. ICC(opr) =CPD xVCC xfIN +ICC/16 (per
circuit)
TEST CIRCUIT =ZOUTof pulse generator (typically 50Ω)
TEST CIRCUIT AND WAVEFORM SYMBOL VALUE