74ALVCH162244TX ,Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26 Ohm Series Resistor in OutputsFunctional DescriptionThe 74ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs ..
74ALVCH162245DGG ,16-bit bus transceiver with direction pin and 30ohm termination resistor 3-StatePIN CONFIGURATION• Wide supply voltage range of 1.2V to 3.6V48 1OE1DIR 1• Complies with JEDEC stand ..
74ALVCH162245DL ,16-bit bus transceiver with direction pin and 30ohm termination resistor 3-StateINTEGRATED CIRCUITS74ALVCH16224516-bit bus transceiver with direction pinand 30Ω termination resist ..
74ALVCH162245DL ,16-bit bus transceiver with direction pin and 30ohm termination resistor 3-StatePIN CONFIGURATION• Wide supply voltage range of 1.2V to 3.6V48 1OE1DIR 1• Complies with JEDEC stand ..
74ALVCH162260GRG4 ,12-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs 56-TSSOP -40 to 85LOGIC DIAGRAM (POSITIVE LOGIC)2LE1B27LE2B30LEA1B55LEA2B56OE2B29OE1B1OEA28SELG1C1823A1 1B111D1C162B1 ..
74ALVCH162373GRE4 ,16-Bit Transparent D-Type Latch with 3-State Outputs 48-TSSOP -40 to 85MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)MIN MAX UNITV Supp ..
74HC4520 ,Dual 4-bit synchronous binary counter
74HC4520 ,Dual 4-bit synchronous binary counter
74HC4520D ,74HC/HCT4520; Dual 4-bit synchronous binary counterAPPLICATIONSThe 74HC/HCT4520 are dual 4-bit internally synchronousbinary counters with an active HI ..
74HC4520N ,Dual 4-bit synchronous binary counterINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC4538 ,Dual Precision Monostable Multivibrator(Retriggerable, Resettable)Maximum Ratings are those values beyond which damage to the device may occurÎ .Functional operation ..
74HC4538D ,Dual retriggerable precision monostable multivibratorINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74ALVCH162244TX
Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26 Ohm Series Resistor in Outputs
74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26Ω Series Resistor in Outputs September 2001 Revised February 2002 74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26Ω Series Resistor in Outputs General Description Features The ALVCH162244 contains sixteen non-inverting buffers1.65V to 3.6V V supply operation CC with 3-STATE outputs to be employed as a memory and 3.6V tolerant control inputs and outputs address driver, clock driver, or bus oriented transmitter/ Bushold on data inputs eliminates the need for external receiver. The device is nibble (4-bit) controlled. Each nibble pull-up/pull-down resistors has separate 3-STATE control inputs which can be shorted 26Ω series resistors in outputs together for full 16-bit operation. t The ALVCH162244 data inputs include active bushold cir- PD cuitry, eliminating the need for external pull-up resistors to 4.2 ns max for 3.0V to 3.6V V CC hold unused or floating data inputs at a valid logic level 4.9 ns max for 2.3V to 2.7V V CC The 74ALVCH162244 is also designed with 26Ω series 7.6 ns max for 1.65V to 1.95V V resistors in the outputs. This design reduces line noise in CC applications such as memory address drivers, clock driv-Uses patented noise/EMI reduction circuitry ers, and bus transceivers/transmitters. Latch-up conforms to JEDEC JED78 The 74ALVCH162244 is designed for low voltage (1.65V to ESD performance: 3.6V) V applications with output capability up to 3.6V. CC Human body model > 2000V The 74ALVCH162244 is fabricated with an advanced Machine model > 200V CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Ordering Code: Package Order Number Package Description Number 74ALVCH162244T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) n I –I Bushold Inputs 0 15 O –O Outputs 0 15 © 2002 DS500632
