74ALVC573BQ ,Octal D-type transparent latch; 3-stateLogic diagram (one latch)D0 D1 D2 D3 D4 D5 D6 D7D Q D Q D Q D Q D Q D Q D Q D QLATCH LATCH LATCH LA ..
74ALVC573BQ ,Octal D-type transparent latch; 3-stateINTEGRATED CIRCUITSDATA SHEET74ALVC573Octal D-type transparent latch;3-stateProduct specification 20 ..
74ALVC573BQ ,Octal D-type transparent latch; 3-stateFeatures■ Wide supply voltage range from 1.65 V to 3.6 V■ 3.6 V tolerant inputs/outputs■ CMOS low p ..
74ALVC573PW ,Octal D-type transparent latch; 3-stateapplications. A latch enable (LE) inputand an outputs enable (OE) input are common to all latches.W ..
74ALVC574PW ,Octal D-type flip-flop positive edge-trigger 3-stateFEATURES DESCRIPTION• Wide supply voltage range from 1.65 to 3.6 V The 74ALVC574 is a high-performa ..
74ALVC574PW ,Octal D-type flip-flop positive edge-trigger 3-stateFeatures■ Wide supply voltage range from 1.65 V to 3.6 V■ 3.6 V tolerant inputs/outputs■ CMOS low p ..
74HC4351D ,74HC/HCT4351; 8-channel analog multiplexer/demultiplexer with latchINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC4351N ,8-channel analog multiplexer/demultiplexer with latchINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC06 74HC/HCT/HC ..
74HC4352 ,Dual 4-channel analog multiplexer/demultiplexer with latch
74HC4353D ,Triple 2-channel analog multiplexer/demultiplexer with latchGENERAL DESCRIPTIONranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.The 74HC/HCT4353 are hi ..
74HC4511 ,BCD to 7-segment latch/decoder/driver
74HC4511 ,BCD to 7-segment latch/decoder/driver
74ALVC573BQ
74ALVC573; Octal D-type transparent latch; 3-state
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
FEATURES Wide supply voltage range from 1.65to 3.6V Complies with JEDEC standards:
JESD8-7 (1.65to 1.95V)
JESD8-5 (2.3to 2.7V)
JESD8B/JESD36 (2.7to 3.6 V). 3.6 V tolerant inputs and outputs CMOS low power consumption Direct interface with TTL levels (2.7to 3.6V) Power-down mode Latch-up performance exceeds 250 mA ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
DESCRIPTIONThe 74ALVC573 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC573 is an octal D-type transparent latch
featuring separate D-type inputsfor each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
internal latches.
The 74ALVC573 consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the Dn inputs enters the latches. In this condition the
latches aretransparent,i.e.a latch output will change state
each time its corresponding D-input changes.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The 74ALVC573 is functionally identical to the
74ALVC373, but the has a different pin arrangement.
QUICK REFERENCE DATAGND=0 V; Tamb =25 °C.
NotesCPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in Volts;= total load switching outputs;
Σ(CL× VCC2×fo)= sum of the outputs. The condition is VI= GNDto VCC.
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
FUNCTION TABLESee note1
Note H= HIGH voltage level;h= HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;L= LOW voltage level;l= LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;Z= high-impedance OFF-state.
ORDERING INFORMATION
PINNING
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referencedto GND (ground=0 V).
Notes The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC=0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
CHARACTERISTICSAt recommended operating conditions; voltages are referenced to GND (ground=0V).
Notes All typical values are measured at VCC= 3.3 V and Tamb =25 °C. For transceivers, the parameter IOZ includes the input leakage current.
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
CHARACTERISTICS
Note All typical values are measured at Tamb =25 °C.
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
WAVEFORMS
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74AL VC573
